參數(shù)資料
型號(hào): MC145506
廠商: Motorola, Inc.
元件分類: Codec
英文描述: PCM CODEC FILTER MONO CIRCUIT
中文描述: 單聲道的PCM編解碼器濾波器電路
文件頁(yè)數(shù): 10/24頁(yè)
文件大?。?/td> 405K
代理商: MC145506
MC145506
MC145507
MC145508
10
MOTOROLA
of 1.0, such that a 3 dBm0 signal at TxI corresponds to the
peak converter reference voltage as described in the Vref
and RSI pin descriptions. For a 3.15 V reference, the 3 dBm0
input should be 6.3 V peak–to–peak.
+Tx / –Tx
Positive Tx Amplifier Input
Negative Tx Amplifier Input
The Txl pin is the input to the transmit band–pass filter. If
+Tx or –Tx is available, then there is an internal amplifier
preceding the filter whose pins are +Tx, –Tx, and TxI. These
pins allow access to the amplifier terminals to tailor the input
gain with external resistors. The resistors should be in the
range of 10 k
.
POWER SUPPLIES
VDD
Most Positive Power Supply
VDD is typically 5 V to 12 V.
VSS
Most Negative Power Supply
VSS is typically 10 V to 12 V negative of VDD.
For a
±
5 V dual–supply system, the typical power supply
configuration is VDD = 5 V, VSS = –5 V, VLS = 0 V (digital
ground accommodating TTL logic levels), and VAG = 0 V
being tied to system analog ground.
For single–supply applications, typical power supply con-
figurations include:
VDD = 10 V to 12 V
VSS = 0 V
VAG generates a mid supply voltage for referencing all ana-
log signals.
VLS controls the logic levels. This pin should be connected
to VDD for CMOS logic levels from VSS to VDD. This pin
should be connected to digital ground for true TTL logic input
levels referenced to VLS, with HCMOS output levels from VLS
to VDD.
TESTING CONSIDERATIONS (MC145506 ONLY)
An analog test mode is activated by connecting MSI and
CCI to 128 kHz. In this mode, the input of the A/D (the output
of the Tx filter) is available at the PDI pin. This input is direct
coupled to the A/D side of the codec. The A/D is a differential
design. This results in the gain of this input being effectively
attenuated by half. If monitored with a high–impedance buff-
er, the output of the Tx low–pass filter can also be measured
at the PDI pin. This test mode allows independent evaluation
of the transmit low–pass filter and A/D side of the codec. The
transmit and receive channels of these devices are tested
with the codec–filter fully functional.
Figure 1. Test Circuit
* To define RDD when TDD is high Z.
MC145507
VAG
RxO
+Tx
TxI
–Tx
Mu/A
PDI
VSS
VDD
RDD
RCE
RDC
TDC
TDD
TDE
VLS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
16
15
600
5 k
10 k
681
VAG
Rx
Tx
–5 V
CLOCK
ENABLE
51 k
*
5 V
0.1
μ
F
0.1
μ
F
Table 1. MC145506 Options Available by Pin Selection
RSI*
Pin Level
Vref*
Pin Level
Peak–to–Peak Overload Voltage
(Txl, RxO)
VDD
VDD
VAG
VAG
VSS
VSS
VSS
7.56 Vp–p
VAG + VEXT
VSS
VAG + VEXT
VSS
VAG + VEXT
(3.02 x VEXT) Vp–p
5 Vp–p
(2 x VEXT) Vp–p
6.3 Vp–p
(2.52 x VEXT) Vp–p
* On MC145507/08, RSI and Vref are tied internally to VSS.
F
Freescale Semiconductor, Inc.
Go to: www.freescale.com
n
.
相關(guān)PDF資料
PDF描述
MC145507 PCM CODEC FILTER MONO CIRCUIT
MC145508 PCM CODEC FILTER MONO CIRCUIT
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