參數(shù)資料
型號: MC14526BCP
廠商: ON SEMICONDUCTOR
元件分類: 通用總線功能
英文描述: Inverting Fast Synchronous Buck MOSFET Drivers with Enable 14-SOIC
中文描述: 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT DOWN BINARY COUNTER, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 4/12頁
文件大?。?/td> 208K
代理商: MC14526BCP
MC14526B
http://onsemi.com
4
(7.)
(8.)
Output Rise and Fall Time
t
TLH
, t
THL
= (1.5 ns/pF) C
L
+ 25 ns
t
TLH
, t
THL
= (0.75 ns/pF) C
L
+ 12.5 ns
t
TLH
, t
THL
= (0.55 ns/pF) C
L
+ 9.5 ns
t
TLH
,
t
THL
(Figures 4, 5)
5.0
10
15
100
50
40
200
100
80
ns
Propagation Delay Time (Inhibit Used as Negative
Edge Clock)
Clock or Inhibit to Q
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 465 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 197 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 135 ns
t
PLH
,
t
PHL
(Figures 4, 5, 6)
5.0
10
15
550
225
160
1100
450
320
ns
Clock or Inhibit to “0”
t
PLH
, t
PHL
= (1.7 ns/pF) C
L
+ 155 ns
t
PLH
, t
PHL
= (0.66 ns/pF) C
L
+ 87 ns
t
PLH
, t
PHL
= (0.5 ns/pF) C
L
+ 65 ns
5.0
10
15
240
130
100
480
260
200
Propagation Delay Time
Pn to Q
t
PLH
,
t
PHL
(Figures 4, 7)
5.0
10
15
260
120
100
520
240
200
ns
Propagation Delay Time
Reset to Q
t
PHL
(Figure 8)
5.0
10
15
250
110
80
500
220
160
ns
Propagation Delay Time
Preset Enable to “0”
t
PHL
,
t
PLH
(Figures 4, 9)
5.0
10
15
220
100
80
440
200
160
ns
Clock or Inhibit Pulse Width
t
w
(Figures 5, 6)
5.0
10
15
250
100
80
125
50
40
ns
Clock Pulse Frequency (with PE = low)
f
max
(Figures 4, 5, 6)
5.0
10
15
2.0
5.0
6.6
1.5
3.0
4.0
MHz
Clock or Inhibit Rise and Fall Time
t
r
,
t
f
(Figures 5, 6)
5.0
10
15
15
5
4
μ
s
Setup Time
Pn to Preset Enable
t
su
(Figure 10)
5.0
10
15
90
50
40
40
15
10
ns
Hold Time
Preset Enable to Pn
t
h
(Figure 10)
5.0
10
15
30
30
30
– 15
– 5
0
ns
Preset Enable Pulse Width
t
w
(Figure 10)
5.0
10
15
250
100
80
125
50
40
ns
Reset Pulse Width
t
w
(Figure 8)
5.0
10
15
350
250
200
175
125
100
ns
Reset Removal Time
t
rem
(Figure 8)
5.0
10
15
10
20
30
– 110
– 30
– 20
ns
7. The formulas given are for the typical characteristics only at 25 C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
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