參數(shù)資料
型號： MC14526BDW
廠商： ON SEMICONDUCTOR
元件分類： 通用總線功能
英文描述： Presettable 4-Bit Down Counters
中文描述： 4000/14000/40000 SERIES, SYN POSITIVE EDGE TRIGGERED 4-BIT DOWN BINARY COUNTER, PDSO16
封裝： SOIC-16
文件頁數(shù)： 1/12頁
文件大?。?/td> 208K
代理商： MC14526BDW
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
1
Publication Order Number:
MC14526B/D
The MC14526B binary counter is constructed with MOS P–channel
and N–channel enhancement mode devices in a monolithic structure.
This device is presettable, cascadable, synchronous down counter
with a decoded “0” state output for divide–by–N applications. In
single stage applications the “0” output is applied to the Preset Enable
input. The Cascade Feedback input allows cascade divide–by–N
operation with no additional gates required. The Inhibit input allows
disabling of the pulse counting function. Inhibit may also be used as a
negative edge clock.
This complementary MOS counter can be used in frequency
synthesizers, phase–locked loops, and other frequency division
applications requiring low power dissipation and/or high noise
immunity.
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge–Clocked Design — Incremented on Positive Transition
of Clock or Negative Transition of Inhibit
Asynchronous Preset Enable
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS
(Voltages Referenced to V
SS
) (Note 2.)
Symbol
Parameter
Value
Unit
V
DD
DC Supply Voltage Range
–0.5 to +18.0
V
V
in
, V
out
Input or Output Voltage Range
(DC or Transient)
–0.5 to V
DD
+ 0.5
V
I
in
, I
out
Input or Output Current
(DC or Transient) per Pin
±
10
mA
P
D
Power Dissipation,
per Package (Note 3.)
500
mW
T
A
Operating Temperature Range
–55 to +125
°
C
T
stg
Storage Temperature Range
–65 to +150
°
C
T
L
Lead Temperature
(8–Second Soldering)
260
°
C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
(V
in
or V
out
)
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either V
SS
or V
DD
). Unused outputs must be left open.
http://onsemi.com
A
WL or L
YY or Y
WW or W = Work Week
= Assembly Location
= Wafer Lot
= Year
Device
Package
Shipping
ORDERING INFORMATION
MC14526BCP
PDIP–16
2000/Box
MC14526BDW
SOIC–16
47/Rail
MARKING
DIAGRAMS
16
1
PDIP–16
P SUFFIX
CASE 648
MC14526BCP
AWLYYWW
MC14526BDWR2
SOIC–16
1000/Tape & Reel
SOIC–16
DW SUFFIX
CASE 751G
1
16
14526B
AWLYYWW
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
SOEIAJ–16
F SUFFIX
CASE 966
1
16
MC14526B
AWLYWW
MC14526BF
SOEIAJ–16
See Note 1.
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