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參數(shù)資料
| 型號(hào)： | MC10H680 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | dual supply 4-Bit differential ECL bus to TTL bus transceiver(雙電源4位差分ECL總線到TTL總線收發(fā)器) |
| 中文描述： | 雙電源4位差動(dòng)ECL巴士與TTL總線收發(fā)器（雙電源4位差分ECL總線到的TTL總線收發(fā)器） |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 132K |
| 代理商： | MC10H680 |
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 7
1
Publication Order Number:
MC10H680/D
The MC10H/100H680 is a dual supply 4–bit differential ECL bus to
TTL bus transceiver. It is designed to allow the system designer to no
longer be limited in bus speed associated with standard TTL busses.
Using a differential ECL Bus will increase the frequency of operation
and increase noise immunity.
Both the TTL and the ECL ports are capable of driving a bus. The
ECL outputs have the ability to drive 25
, allowing both ends of the
bus line to be terminated in the characteristic impedance of 50
. The
TTL outputs are specified to source 15 mA and sink 48 mA, allowing
the ability to drive highly capacitive loads.
The ECL output levels are VOH approximately equal to –1.0 V and
VOL cutoff equal to –2.0 V (VTT). When the ECL ports are disabled
both EIOx and EIOxB go to the VOL cutoff level. The ECL input
receivers have special circuitry which detects this disabled condition,
prevents oscillation, and forces the TTL output to the low state. The
noise margin in this disabled state is greater than 600 mV. Multiple
ECL VCCO pins are utilized to minimize switching noise.
The TTL ports have standard levels. The TTL input receivers have
PNP input devices to significantly reduce loading. Multiple TTL
power and ground pins are utilized to minimize switching noise.
The control pins (EDIR and ECEB) of the 10H version is
compatible with MECL 10H ECL logic levels. The control pins of the
100H version are compatible with 100K levels.
Differential ECL Bus (25
) I/O Ports
High Drive TTL Bus I/O Ports
Extra TTL and ECL Power/Ground Pins to Minimize Switching
Noise
Dual Supply
Direction and Chip Enable Control Pins
Pinout: 28–Lead PLCC
(Top View)
T
G
V
G
T
T
E
E
E
E
E
V
V
V
1
5
6
7
8
9
10
11
25
24
23
22
21
20
19
26
27
28
2
3
4
12
13
14
15
16
17
18
T101
GT2
VT1
GT1
TIO0
TDIR
EDIR
EIO3B
VCCO4
EIO3
VCCE
EIO2B
VCCO3
EIO2
http://onsemi.com
Device
Package
Shipping
ORDERING INFORMATION
MC10H680FN
PLCC–28
37 Units/Rail
MARKING
DIAGRAM
A
WL = Wafer Lot
YY
= Year
WW = Work Week
= Assembly Location
PLCC–28
FN SUFFIX
CASE 776
10H680
AWLYYWW
1
MC100H680FN
PLCC–28
37 Units/Rail
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC10H680FN | 功能描述:總線收發(fā)器 4-Bit Diff ECL / TTL RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| MC10H680FNG | 功能描述:總線收發(fā)器 4-Bit Diff ECL / TTL Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| MC10H680FNR2 | 功能描述:總線收發(fā)器 4-Bit Diff ECL / TTL RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| MC10H680FNR2G | 功能描述:總線收發(fā)器 4-Bit Diff ECL / TTL Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel |
| MC10LVEP11D | 功能描述:時(shí)鐘緩沖器 2.5V/3.3V ECL 1:2 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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