參數(shù)資料
型號(hào): MC10EP451FA
廠商: ON SEMICONDUCTOR
元件分類(lèi): 通用總線(xiàn)功能
英文描述: 3.3V / 5VECL 6-Bit Differential Register with Master Reset
中文描述: 10E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQFP32
封裝: LQFP-32
文件頁(yè)數(shù): 6/10頁(yè)
文件大小: 91K
代理商: MC10EP451FA
MC10EP451, MC100EP451
http://onsemi.com
6
Table 9. 100EP DC CHARACTERISTICS, NECL
V
CC
= 0 V, V
EE
= 5.5 V to 3.0 V (Note 17)
40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
I
EE
Power Supply Current
85
105
135
85
105
135
85
105
135
mA
V
OH
Output HIGH Voltage (Note 18)
1145
1020
895
1145
1020
895
1145
1020
895
mV
V
OL
Output LOW Voltage (Note 18)
1945
1820
1695
1945
1820
1695
1945
1820
1695
mV
V
IH
Input HIGH Voltage (SingleEnded)
1225
880
1225
880
1225
880
mV
V
IL
Input LOW Voltage (SingleEnded)
1945
1625
1945
1625
1945
1625
mV
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 19)
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
EE
+2.0
0.0
V
I
IH
Input HIGH Current
150
150
150
A
I
IL
Input LOW Current
0.5
0.5
0.5
A
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
17.Input and output parameters vary 1:1 with V
CC
.
18.All loading with 50 to V
CC
2.0 V.
19.V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
Table 10. AC CHARACTERISTICS
V
CC
= 0 V; V
EE
= 3.0 V to 5.5 V or V
CC
= 3.0 V to 5.5 V; V
EE
= 0 V (Note 20)
40
°
C
25
°
C
85
°
C
Symbol
Characteristic
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
V
OUTpp
Output Voltage Amplitude @ 3 GHz
(Figure 3) (Note 21)
540
670
520
650
450
580
GHz
t
PLH
,
t
PHL
Propagation Delay to
Output Differential
CLK to Q, Q
MR to Q, Q
330
430
430
530
530
630
350
450
450
550
550
650
390
490
490
590
590
690
ps
t
RR
Reset Recovery
MR to CLK
240
145
250
150
260
160
ps
t
S
t
H
Setup Time
Hold Time
D to CLK
CLK to D
80
80
40
40
80
80
40
40
80
80
40
40
ps
t
PW
Minimum Pulse Rate
MR
400
400
400
ps
t
SKEW
WithinDevice Skew (Note 22)
DeviceToDevice Skew (Note 23)
20
35
40
100
20
35
40
100
20
35
40
100
t
JITTER
CLOCK Random Jitter (RMS)
@
3.0 GHz (Figure 3)
0.2
1
0.2
1
0.2
1
ps
t
r
t
f
Output Rise/Fall Times
(20% 80%)
Q, Q
100
100
150
150
250
250
110
110
160
160
260
260
130
130
180
180
280
280
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
20.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to V
CC
2.0 V.
21.V
OL
and V
OH
specifications not guaranteed for F
max
testing.
22.Skew is measured between outputs under identical transitions and conditions on any one device.
23.DeviceToDevice skew for identical transitions at identical V
CC
levels.
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