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參數(shù)資料
| 型號： | MC100LVEL51DR2 |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | 通用總線功能 |
| 英文描述： | Differential Clock D Flip-Flop |
| 中文描述： | 100LVEL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 1/3頁 |
| 文件大?。?/td> | 95K |
| 代理商： | MC100LVEL51DR2 |
SEMICONDUCTOR TECHNICAL DATA
4–1
REV 1
Motorola, Inc. 1996
8/96
The MC100LVEL51 is a differential clock D flip-flop with reset. The
device is functionally equivalent to the EL51 device, but operates from a
low voltage supply. With propagation delays and output transition times
essentially equal to the EL51, the LVEL51 is ideally suited for those
applications which require the ultimate in AC performance at 3.3V VCC.
The reset input is an asynchronous, level triggered signal. Data enters
the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock. The differential clock inputs of the LVEL51 allow the device to
be used as a negative edge triggered flip-flop.
The differential input employs clamp circuitry to maintain stability under
open input conditions. When left open, the CLK input will be pulled down
to VEE and the CLK input will be biased at VCC/2.
475ps Propagation Delay
2.8GHz Toggle Frequency
Operates from –3.3V (or 3.3V) Supply
75k
Internal Input Pulldown Resistors
>2000V ESD Protection
1
2
3
4
5
6
7
8
Q
VEE
VCC
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D
Q
CLK
CLK
R
D
R
Flip-Flop
TRUTH TABLE
D
L
H
X
R
L
L
H
CLK
Z
Z
X
Q
L
H
L
Z = LOW to HIGH Transition
1
8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751-05
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100LVELT23DR2 | 3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator |
| MC100LVELT23DR2G | 3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator |
| MC100LVELT23DG | 3.3 V Dual Differential LVPECL/LVDS to LVTTL Translator |
| MC100LVELT23DT | Replaced by TPS2052B : 0.7A, 2.7-5.5V Dual (1In/ 2Out) Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC 0 to 85 |
| MC100LVELT23DTR2 | Replaced by TPS2052B : 0.7A, 2.7-5.5V Dual (1In/ 2Out) Hi-Side MOSFET, Fault Report, Act-High Enable 8-SOIC 0 to 85 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100LVEL51DR2G | 功能描述:觸發(fā)器 3.3V/5V ECL D-Type w/Diff Clock RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100LVEL51DT | 功能描述:觸發(fā)器 3.3V/5V ECL D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100LVEL51DTG | 功能描述:觸發(fā)器 3.3V/5V ECL D-Type w/Diff Clock RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100LVEL51DTR2 | 功能描述:觸發(fā)器 3.3V/5V ECL D-Type RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
| MC100LVEL51DTR2G | 功能描述:觸發(fā)器 3.3V/5V ECL D-Type w/Diff Clock RoHS:否 制造商:Texas Instruments 電路數(shù)量:2 邏輯系列:SN74 邏輯類型:D-Type Flip-Flop 極性:Inverting, Non-Inverting 輸入類型:CMOS 輸出類型: 傳播延遲時間:4.4 ns 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:X2SON-8 封裝:Reel |
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