SEMICONDUCTOR TECHNICAL DATA
2–144
REV 6
Motorola, Inc. 1996
9/96
The MC10H/100H680 is a dual supply 4–bit differential ECL bus to TTL
bus transceiver. It is designed to allow the system designer to no longer be
limited in bus speed associated with standard TTL busses. Using a
differential ECL Bus will increase the frequency of operation and increase
noise immunity.
Both the TTL and the ECL ports are capable of driving a bus. The ECL
outputs have the ability to drive 25
, allowing both ends of the bus line to be
terminated in the characteristic impedance of 50
. The TTL outputs are
specified to source 15 mA and sink 48 mA, allowing the ability to drive highly
capacitive loads.
The ECL output levels are VOH approximately equal to –1.0 V and VOL
cutoff equal to –2.0 V (VTT). When the ECL ports are disabled both EIOx and
EIOxB go to the VOL cutoff level. The ECL input receivers have special
circuitry which detects this disabled condition, prevents oscillation, and
forces the TTL output to the low state. The noise margin in this disabled state
is greater than 600 mV. Multiple ECL VCCO pins are utilized to minimize
switching noise.
The TTL ports have standard levels. The TTL input receivers have PNP
input devices to significantly reduce loading. Multiple TTL power and ground
pins are utilized to minimize switching noise.
The control pins (EDIR and ECEB) of the 10H version is compatible with
MECL 10H ECL logic levels. The control pins of the 100H version are
compatible with 100K levels.
Differential ECL Bus (25
) I/O Ports
High Drive TTL Bus I/O Ports
Extra TTL and ECL Power/Ground Pins to Minimize
Switching Noise
Dual Supply
Direction and Chip Enable Control Pins
Pinout: 28–Lead PLCC
(Top View)
T
G
V
G
T
T
E
E
E
E
E
VC
V
VC
1
5
6
7
8
9
10
11
25
24
23
22
21
20
19
26
27
28
2
3
4
12
13
14
15
16
17
18
T101
GT2
VT1
GT1
TIO0
TDIR
EDIR
EIO3B
VCCO4
EIO3
VCCE
EIO2B
VCCO3
EIO2
PIN DESCRIPTIONS
Pin
Symbol
Function
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
GT1
TIO0
TDIR
EDIR
EIO0
VCCO1
EIO0B
VEE
EIO1
VCCO2
EIO1B
EIO2
VCCO3
EIO2B
VCCE
EIO3
VCCO4
EIO3B
ECEB
TCEB
TIO3
GT4
VT2
GT3
TIO2
TIO1
GT2
VT1
TTL Ground 1
TTL I/O Bit 0
TTL Direction Control
ECL Direction Control
ECL I/O Bit 0
ECL VCC 1 (0V) – Outputs
ECL I/O Bit 0 Bar
ECL Supply (–5.2/–4.5V)
ECL I/O Bit 1
ECL VCC 2 (0V) – Outputs
ECL I/O Bit 1 Bar
ECL I/O Bit 2
ECL VCC 3 (0V) – Outputs
ECL I/O Bit 2 Bar
ECL VCC (0V)
ECL I/O Bit 3
ECL VCC 4 (0V) – Outputs
ECL I/O Bit 3 Bar
ECL Chip Enable Bar Control
TTL Chip Enable Bar Control
TTL I/O Bit 3
TTL Ground 4
TTL Supply 2 (5V)
TTL Ground 3
TTL I/O Bit 2
TTL I/O Bit 1
TTL Ground 2
TTL Supply 1 (5V)
FN SUFFIX
PLASTIC PACKAGE
CASE 776–02