- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄354433 > MC100E104 (ON SEMICONDUCTOR) QUINT 2-INPUT AND/NAND GATE PDF資料下載
參數(shù)資料
| 型號(hào)： | MC100E104 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | QUINT 2-INPUT AND/NAND GATE |
| 中文描述： | 昆鵬2輸入和/與非門 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 226K |
| 代理商： | MC100E104 |
Advanced Clock Drivers Devices
Freescale Semiconductor
5
MC100ES6210
Figure 3. MC100ES6210 AC Test Reference
Table 6. AC Characteristics (ECL: VEE = –3.3 V ± 5% or VEE = –2.5 V ± 5%, VCC = GND) or
(PECL: VCC = 3.3 V ± 5% or VCC = 2.5 V ± 5%, VEE = GND, TJ = 0°C to +110°C)(1) (2)
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50
to VTT.
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Clock Input Pair CLKA, CLKA, CLKB, CLKB (PECL or ECL differential signals)
VPP
Differential Input Voltage(3) (peak-to-peak)
3. VPP (AC) is the minimum differential ECL/PECL input voltage swing required to maintain AC characteristics including tPD and
device-to-device skew.
0.3
1.3
V
VCMR
Differential Input Crosspoint Voltage(4)
PECL
ECL
4. VCMR (AC) is the crosspoint of the differential ECL/PECL input signal. Normal AC operation is obtained when the crosspoint is within the
VCMR (AC) range and the input swing lies within the VPP (AC) specification. Violation of VCMR (AC) or VPP (AC) impacts the device
propagation delay, device and part-to-part skew.
1.2
VEE + 1.2
VCC – 0.3
–0.3 V
V
ECL Clock Outputs (Q0–9, Q0–9)
fCLK
Input Frequency
0
3000
MHz Differential
tPD
Propagation Delay
CLKA to QAx or CLKB to QBx
175
260
350
ps
Differential
VO(P-P)
Differential Output Voltage (peak-to-peak)
fO < 1.1 GHz
fO < 2.5 GHz
fO < 3.0 GHz
0.45
0.35
0.20
0.70
0.55
0.35
V
tsk(O)
Output-to-Output Skew (per bank)
13
30
ps
Differential
tsk(PP)
Output-to-Output Skew (part-to-part)
175
ps
Differential
tJIT(CC)
Output Cycle-to-Cycle Jitter
1
ps
tSK(P)
DCQ
Output Pulse Skew(5)
Output Duty Cycle
fREF < 0.1 GHz
fREF < 1.0 GHz
5. Output pulse skew is the absolute difference of the propagation delay times: | tPLH – tPHL |.
49.5
45.0
50
50.5
55.0
ps
%
DCREF = 50%
tr, tf
Output Rise/Fall Time
30
250
ps
20% to 80%
Differential Pulse
Generator
Z = 50
RT = 50
ZO = 50
DUT
MC100ES6210
VTT
RT = 50
ZO = 50
VTT
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MC100E107 | QUINT 2-INPUT XOR/XNOR GATE |
| MC100E111 | 1:9 DIFFERENTIAL CLOCK DRIVER |
| MC100E112 | QUAD DRIVER |
| MC100EP52 | 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Data and Clock D Flip-Flop |
| MC100EP52D | 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination Data and Clock D Flip-Flop |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC100E104 E27G WAF | 制造商:ON Semiconductor 功能描述: |
| MC100E104FN | 功能描述:邏輯門 5V ECL Quint 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC100E104FNG | 功能描述:邏輯門 5V ECL Quint 2-Input AND/NAND RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
| MC100E104FNG | 制造商:ON Semiconductor 功能描述:AND/NAND GATE LOGIC IC |
| MC100E104FNR2 | 功能描述:邏輯門 5V ECL Quint 2-Input RoHS:否 制造商:Texas Instruments 產(chǎn)品:OR 邏輯系列:LVC 柵極數(shù)量:2 線路數(shù)量（輸入/輸出）:2 / 1 高電平輸出電流:- 16 mA 低電平輸出電流:16 mA 傳播延遲時(shí)間:3.8 ns 電源電壓-最大:5.5 V 電源電壓-最小:1.65 V 最大工作溫度:+ 125 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DCU-8 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。