參數(shù)資料
型號: MBM30LV0064-PFTR
廠商: FUJITSU LTD
元件分類: DRAM
英文描述: 64M (8M X 8) BIT NAND-type
中文描述: 8M X 8 FLASH 3.3V PROM, 7000 ns, PDSO40
封裝: 0.80 MM PITCH, PLASTIC, REVERSE, TSOP2-44/40
文件頁數(shù): 7/43頁
文件大?。?/td> 397K
代理商: MBM30LV0064-PFTR
MBM30LV0064
7
I
DEVICE BUS OPERATIONS
*1:H: V
IH
, L: V
IL
, X: V
IH
or V
IL
*2:WP should be biased to CMOS high or CMOS low for standby.
*3:When SE is high, spare area is deselected.
*4:If 50h command is input and read/program operation is executed only for spare area, SE must be low at the
command/address input.
*: H: V
IH
, L: V
IL
, X: V
IH
or V
IL
Table 2 Operation Table
*1
Mode
CLE
ALE
CE
WE
RE
SE
WP
Read
Mode
Command Input
H
L
L
H
X
*4
X
Address Input (3 clock)
L
H
L
H
X
*4
X
During Read (Busy)
L
L
L
H
H
L/H
*3
X
Sequential Read & Data Output
L
L
L
H
L/H
*3
X
Program/
Erase
Mode
Command Input
H
L
L
H
X
*4
H
Address Input (2 or 3 clock)
L
H
L
H
X
*4
H
Data Input
L
L
L
H
L/H
*3
H
During Program (Busy)
X
X
X
X
X
L/H
*3
H
During Erase (Busy)
X
X
X
X
X
X
H
Write Protect
X
X
X
X
X
X
L
Stand-by
X
X
H
X
X
0 V/V
CC*2
0 V/V
CC*2
Table 3 Read Mode Operation Status *
Operation
CLE
ALE
CE
WE
RE
I/O0 to I/O7
Power Supply
Output Select
L
L
L
H
L
Data Output
Active
Output Deselect
L
L
L
H
H
High Impedance
Active
Standby
X
X
H
X
X
High Impedance
Standby
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