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參數(shù)資料
| 型號： | MBM29PL12LM |
| 廠商： | Fujitsu Limited |
| 英文描述： | FLASH MEMORY 128 M (16M ?8/8M ?16) BIT |
| 中文描述： | 快閃記憶體128米（1,600？8/8M？16）位 |
| 文件頁數(shù)： | 26/72頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | MBM29PL12LM |
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MBM29PL12LM
10
26
Page Mode Read
The device is capable of fast read access for random locations within limited address location called page. The
page size of the device is 8 bytes / 4 words, within the appropriate page being selected by the higher address
bits A
22
to A
2
and the address bits A
1
to A
0
in Word mode ( A
1
to A
-1
in Byte mode) determining the specific word
within that page. This is an asynchronous operation with the microprocessor supplying the specific word location.
The initial page access is equal to the random access (t
ACC
) and subsequent Page read access (as long as the
locations specified by the microprocessor fall within that Page) is equivalent to the page address access
time(t
PACC
). Here again, CE selects the device and OE is the output control and should be used to gate data to
the output pins if the device is selected. Fast Page mode, accesses are obtained by keeping A
20
to A
2
constant
and changing A
1
and A
0
in Word mode ( A
1
to A
-1
in Byte mode ) to select the specific word within that Page.
Refer to “Read Operation Timing Diagram” in
■
TIMING DIAGRAM.
Output Disable
With the OE input at logic high level (V
IH
), output from the devices are disabled. This may cause the output pins
to be in a high impedance state.
Write
Device erasure and programming are accomplished via the command register. The contents of the register serve
as inputs to the internal state machine. The state machine outputs dictate the device function.
The command register itself does not occupy any addressable memory location. The register is a latch used to
store the commands, along with the address and data information needed to execute the command. The com-
mand register is written by bringing WE to V
IL
, while CE is at V
IL
and OE is at V
IH
. Addresses are latched on the
falling edge of WE or CE, whichever starts later; while data is latched on the rising edge of WE or CE, whichever
starts first. Standard microprocessor write timings are used.
Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters.
Sector Group Protection
The device features hardware sector group protection. This feature will disable both program and erase opera-
tions in any combination of 70 sector groups of memory.See “Sector Group Address Table (MBM29PL12LM)”
in
■
DEVICE BUS OPERATION. The user‘s side can use the sector group protection using programming equip-
ment. The device is shipped with all sector groups that are unprotected.
To activate it, the programming equipment must force V
ID
on address pin A
9
and control pin OE, CE = V
IL
and
(A
6
, A
3
, A
2
, A
1
, A
0
)
=
(0, 0, 0, 1, 0) . The sector group addresses (A
22
, A
21
, A
20
, A
19
, A
18
, A
17
, A
16
, and A
15
) should
be set to the sector to be protected. “Sector Group Address Table (MBM29PL12LM)” in
■
DEVICE BUS OPER-
ATION defines the sector address for each of the 70 individual sectors, and “Sector Group Address Table
(MBM29PL12LM)” in
■
DEVICE BUS OPERATION defines the sector group address for each of the twenty-four
(24) individual group sectors. Programming of the protection circuitry begins on the falling edge of the WE pulse
and is terminated with the rising edge of the same. Sector group addresses must be held constant during the
WE pulse. See “Sector Group Protection Timing Diagram” in
■
TIMING DIAGRAM and “Sector Group Protection
Algorithm” in
■
FLOW CHART for sector group protection timing diagram and algorithm.
To verify programming of the protection circuitry, the programming equipment must force V
ID
on address pin A
9
with CE and OE at V
IL
and WE at V
IH
. Scanning the sector group addresses (A
22
, A
21
, A
20
, A
19
, A
18
, A
17
, A
16
, and
A
15
) while (A
6
, A
3
, A
2
, A
1
, A
0
) = (0, 0, 0, 1, 0) will produce a logical “1” code at device output DQ
0
for a protected
sector. Otherwise the device will produce “0” for unprotected sectors. In this mode, the lower order addresses,
except for A
0
, A
1
, A
2
, A
3
, and A
6
can be either High or Low. Address locations with A
1
= V
IL
are reserved for
Autoselect manufacturer and device codes. A
-1
requires applying to V
IL
on Byte mode.
It is also possible to determine if a sector group is protected in the system by writing an Autoselect command.
Performing a read operation at the address location XX02h, where the higher order addresses(A
22
, A
21
, A
20
, A
19
,
A
18
, A
17
, A
16
, and A
15
) are the desired sector group address will produce a logical “1” at DQ
0
for a protected sector
group. See “MBM29PL12LM User Bus Operations (Word Mode : BYTE
=
V
IH
) and “Sector Group Protection
Verify Autoselect Codes” in
■
DEVICE BUS OPERATION for Autoselect codes.
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