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參數(shù)資料
| 型號(hào)： | MBM29PL12LM10PCN |
| 廠商： | FUJITSU LTD |
| 元件分類： | DRAM |
| 英文描述： | FLASH MEMORY 128 M (16M ?8/8M ?16) BIT |
| 中文描述： | 8M X 16 FLASH 3V PROM, 100 ns, PDSO56 |
| 封裝： | PLASTIC, TSOP1-56 |
| 文件頁數(shù)： | 30/72頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | MBM29PL12LM10PCN |
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MBM29PL12LM
10
30
graming operation is completed when the data on DQ7 is equivalent to the data written to this bit at which time
the device returns to the read mode ( See "Hardware Sequence Flags").
The write-buffer programming operation can be suspended/resumed using the standard program suspend/
resume commands.
Once the write buffer programming is set, the system must then write the “Program Buffer to Flash” command
at the Sector Address. Any other address/data combination will abort the Write Buffer Programming operation
and the device will continue busy state.
The Write Buffer Programming Sequence can be ABORTED by doing the following :
Different Sector Address is asserted.
Write data other than the “Program Buffer to Flash" command after the specified number of “data load” cycles.
A “Write-to-Buffer-Abort Reset” command sequence must be written to the device to return to read mode. (See
“MBM29PL12LM Standard Command Definitions” in
■
DEVICE BUS OPERATION for details on this command
sequence.)
Chip Erase
Chip erase is a 6 bus cycle operation. It begins two “unlock” write cycles followed by writing the “set-up” command,
and two “unlock” write cycles followed by the chip erase command which invokes the Embedded Erase algorithm.
The device does not require the user to program the device prior to erase. Upon executing the Embedded Erase
Algorithm the devices automatically programs and verifies the entire memory for an all 0 data pattern prior to
electrical erase (Preprogram function). The system is not required to provide any controls or timings during these
operations.
The system can determine the erase operation status by using DQ
7
(Data Polling), DQ
6
(Toggle Bit) and DQ
2
(Toggle Bit
II) or RY/BY output signal
. The chip erase begins on the rising edge of the last CE or WE, whichever
happens first from last command sequence and completes when the data on DQ
7
is “1” at which time the device
returns to read mode.
Sector Erase
Sector erase is a 6 bus cycle operation. There are two “unlock” write cycles. These are followed by writing the
“set-up” command. Two more “unlock” write cycles are then followed by the Sector Erase command.
Multiple sectors may be erased concurrently by writing the same six bus cycle operations. This sequence is
followed by writes of the Sector Erase command to addresses in other sectors desired to be concurrently erased.
The time between writes must be less than Erase Time-out time(t
TOW
). Otherwise that command will not be
accepted and erasure will not start. It is recommended that processor interrupts be disabled during this time to
guarantee this condition. The interrupts can reoccur after the last Sector Erase command is written. A time-out
of “t
TOW
” from the rising edge of last CE or WE, whichever happens first, will initiate the execution of the Sector
Erase command(s). If another falling edge of CE or WE, whichever happens first occurs within the “t
TOW
” time-
out window the timer is reset (monitor DQ
3
to determine if the sector erase timer window is still open, see section
DQ
3
, Sector Erase Timer). Resetting the devices once execution has begun will corrupt the data in the sector.
In that case, restart the erase on those sectors and allow them to complete (refer to the Write Operation Status).
Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 255).
Sector erase does not require the user to program the devices prior to erase. The devices automatically program
all memory locations in the sector(s) to be erased prior to electrical erase using the Embedded Erase Algorithm.
When erasing a sector, the remaining unselected sectors remain unaffected. The system is not required to
provide any controls or timings during these operations.
The system can determine the status of the erase operation by using DQ
7
(Data Polling), DQ
6
(Toggle Bit) or
RY/BY
.
The sector erase begins after the “t
TOW
” time-out from the rising edge of CE or WE whichever happens first for
the last sector erase command pulse and completes when the data on DQ
7
is “1” (see Write Operation Status
section), at which the devices return to the read mode. Data polling and Toggle Bit must be performed at an
address within any of the sectors being erased.
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