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參數(shù)資料
| 型號： | MBM29PL12LM10PBT |
| 廠商： | Fujitsu Limited |
| 英文描述： | FLASH MEMORY 128 M (16M ?8/8M ?16) BIT |
| 中文描述： | 快閃記憶體128米（1,600？8/8M？16）位 |
| 文件頁數(shù)： | 35/72頁 |
| 文件大?。?/td> | 1036K |
| 代理商： | MBM29PL12LM10PBT |
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MBM29PL12LM
10
35
DQ
7
Data Polling
The devices feature Data Polling as a method to indicate to the host that the Embedded Algorithms are in
progress or completed. During the Embedded Program Algorithm, an attempt to read devices will produce
reverse data last written to DQ
7
. Upon completion of the Embedded Program Algorithm, an attempt to read the
device will produce true data last written to DQ
7
. For programming, the Data Polling is valid after the rising edge
of fourth write pulse in the four write pulse sequence. During the Embedded Erase Algorithm, an attempt to read
the device will produce a “0” at the DQ
7
output. Upon completion of the Embedded Erase Algorithm, an attempt
to read device will produce a “1” at the DQ
7
output. The flowchart for Data Polling (DQ
7
) is shown in “Data Polling
Algorithm” in
■
FLOW CHART.
For chip erase and sector erase, the Data Polling is valid after the rising edge of the sixth write pulse in the six
write cycles. Data Polling must be performed at sector addresses of sectors being erased, not protected sectors.
Otherwise, the status may become invalid.
If a program address falls within a protected sector, Data polling on DQ7 is active for approximately 1
μ
s, then
the device returns to read mode. After an erase command sequence is written, if all sectors selected for erasing
are protected, Data Polling on DQ
7
is active for approximately 400
μ
s, then the device returns to read mode. If
not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and
ignores the selected sectors that are protected.
Once the Embedded Algorithm operation is close to being completed, the device data pins (DQ
7
) may change
asynchronously while the output enable (OE) is asserted low. This means that the device is driving status
information on DQ
7
at one instant of time, and then that byte’s valid data the next. Depending on when the system
samples the DQ
7
output, it may read the sequence flag or valid data. Even if the device completes the Embedded
Algorithm operation and DQ
7
has a valid data, the data outputs on DQ
6
to DQ
0
may still be invalid. The valid data
on DQ
7
to DQ
0
will be read on the successive read attempts.
The Data Polling feature is active only during the Embedded Programming Algorithm, Embedded Erase Algo-
rithm, Erase Suspend mode or sector erase time-out.
See “Data Polling during Embedded Algorithm Operation Timing Diagram” in
■
TIMING DIAGRAM for the Data
Polling timing specifications and diagram.
DQ
6
Toggle Bit I
The device also feature the “Toggle Bit I” as a method to indicate to the host system that the Embedded Algorithms
are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (CE or OE toggling) data
from the devices will result in DQ
6
toggling between 1 and 0. Once the Embedded Program or Erase Algorithm
cycle is completed, DQ
6
will stop toggling and valid data will be read on the next successive attempts. During
programming, the Toggle Bit I is valid after the rising edge of the fourth write pulse in the four write cycles. For
chip erase and sector erase, the Toggle Bit I is valid after the rising edge of the sixth write pulse in the six write
cycles. The Toggle Bit I is active during the sector time out.
In programm operation, if the sector being written to is protected, the Toggle bit will toggle for about 1
μ
s and
then stop toggling with the data unchanged. In erase, the device will erase all the selected sectors except for
the protected ones. If all selected sectors are protected, the chip will toggle the Toggle bit for about 400
μ
s and
then drop back into read mode, having data kept remained.
Either CE or OE toggling will cause the DQ
6
to toggle. See “Toggle Bit l Timing Diagram during Embedded
Algorithm Operations” in
■
TIMING DIAGRAM for the Toggle Bit I timing specifications and diagram.
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