參數(shù)資料
型號(hào)： MBM29DL32TF70TN
廠商： FUJITSU LTD
元件分類(lèi)： PROM
英文描述： 2M X 16 FLASH 3V PROM, 70 ns, PDSO48
封裝： PLASTIC, TSOP1-48
文件頁(yè)數(shù)： 23/70頁(yè)
文件大?。?/td> 862K
代理商： MBM29DL32TF70TN
MBM29DL32TF/BF-70
3
s FEATURES
0.17
m Process Technology
Two-bank Architecture for Simultaneous Read/Program and Read/Erase
FlexBankTM
Bank A : 4 Mbit (8 KB
× 8 and 64 KB × 7)
Bank B : 12 Mbit (64 KB
× 24)
Bank C : 12 Mbit (64 KB
× 24)
Bank D : 4 Mbit (64 KB
× 8)
Two virtual Banks are chosen from the combination of four physical banks (Refer to “FlexBankTM Architecture
Table” and “Example of Virtual Banks Combination Table” in sFUNCTIONAL DESCRIPTION)
Host system can program or erase in one bank, and then read immediately and simultaneously from the other
bank with zero latency between read and write operations.
Read-while-erase
Read-while-program
Single 3.0 V Read, Program, and Erase
Minimizes system level power requirements
Compatible with JEDEC-standard Commands
Uses same software commands as E2PROMs
Compatible with JEDEC-standard World-wide Pinouts
48-pin TSOP (1) (Package suffix : TN
Normal Bend Type)
48-ball FBGA (Package suffix : PBT)
Minimum 100,000 Program/Erase Cycles
High Performance
70 ns maximum access time
Sector Erase Architecture
Eight 4 K word and sixty-three 32 K word sectors in word mode
Eight 8 K byte and sixty-three 64 K byte sectors in byte mode
Any combination of sectors can be concurrently erased. Also supports full chip erase.
Boot Code Sector Architecture
T
= Top sector
B
= Bottom sector
HiddenROM Region
256 byte of HiddenROM, accessible through a new “HiddenROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
WP/ACC Input Pin
At VIL, allows protection of “outermost” 2
× 8 bytes on boot sectors, regardless of sector group protection/
unprotection status.
At VACC, increases program performance
Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
Data Polling and Toggle Bit feature for detection of program or erase cycle completion
Ready/Busy Output (RY/BY)
Hardware method for detection of program or erase cycle completion
Automatic Sleep Mode
When addresses remain stable, automatically switch themselves to low power mode.
(Continued)
相關(guān)PDF資料
PDF描述
MBM29F800TA-70PFTN-E1 512K X 16 FLASH 5V PROM, 70 ns, PDSO48
MBR-2051-1B5T 51 CONTACT(S), MALE, D MICROMINIATURE CONNECTOR, SOLDER, PLUG
MBR-2069-0A1T 69 CONTACT(S), MALE, D MICROMINIATURE CONNECTOR, SOLDER, PLUG
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