參數(shù)資料
型號： MB9BF617TBGL
廠商： FUJITSU LTD
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, RISC MICROCONTROLLER, PBGA192
封裝： 12 X 12 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, FBGA-192
文件頁數(shù)： 10/132頁
文件大小： 1257K
代理商： MB9BF617TBGL
107
FUJITSU SEMICONDUCTOR CONFIDENTIAL
r1.1
MB9B610T Series
DS706-00014-0v01-E
(12) I
2C timing
(Vcc = 2.7V to 5.5V, Vss = 0V, Ta = - 40
°C to + 85°C )
Typical
mode
High-speed
mode
Parameter
Symbol Conditions
Min
Max
Min
Max
Unit Remarks
SCL clock frequency
fSCL
0
100
0
400
kHz
(Repeated) START condition
hold time
SDA
↓ → SCL ↓
tHDSTA
4.0
-
0.6
-
μs
SCLclock "L" width
tLOW
4.7
-
1.3
-
μs
SCLclock "H" width
tHIGH
4.0
-
0.6
-
μs
(Repeated) START setup time
SCL
↑ → SDA ↓
tSUSTA
4.7
-
0.6
-
μs
Data hold time
SCL
↓ → SDA ↓ ↑
tHDDAT
0
3.45*2
0
0.9*3
μs
Data setup time
SDA
↓ ↑ → SCL ↑
tSUDAT
250
-
100
-
ns
STOP condition setup time
SCL
↑ → SDA ↑
tSUSTO
4.0
-
0.6
-
μs
Bus free time between
"STOP condition" and
"START condition"
tBUF
CL = 30pF,
R = (Vp/IOL)
*1
4.7
-
1.3
-
μs
8MHz ≤
tCYCP ≤ 40MHz
2 tCYCP
*4
-
2 tCYCP
*4
-
ns *5
40MHz
<
tCYCP ≤ 60MHz
3 tCYCP
*4
-
3 tCYCP
*4
-
ns *5
Noise filter
tSP
60MHz
<
tCYCP ≤ 72MHz
4 tCYCP
*4
-
4 tCYCP
*4
-
ns *5
*1:
R and C represent the pull-up resistance and load capacitance of the SCL and SDA lines, respectively. Vp
indicates the power supply voltage of the pull-up resistance and IOL indicates VOL guaranteed current.
*2:
The maximum tHDDAT must satisfy that it does not extend at least "L" period (tLOW) of device's SCL
signal.
*3:
A high-speed mode I2C bus device can be used on a standard mode I2C bus system as long as the device
satisfies the requirement of "tSUDAT ≥ 250 ns".
*4:
tCYCP is the APB bus clock cycle time.
About the APB bus number which I2C is connected to, see chapter " BLOCK DIAGRAM" in this data
sheet.
To use I2C, set the peripheral bus clock at 8 MHz or more.
*5:
The number of steps of the noise filter can be changed with register settings.
Change the number of the noise filter steps according to APB2 bus clock frequency.
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