參數資料
型號： MB9AF312LPMC
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP64
封裝： 0.65 MM PITCH, PLASTIC, LQFP-64
文件頁數： 72/114頁
文件大?。?/td> 1357K
代理商： MB9AF312LPMC
ATmega48PA/88PA/168PA [DATASHEET]
9223F–AVR–04/14
60
13.2
Register Description
13.2.1 EICRA – External Interrupt Control Register A
The external interrupt control register A contains control bits for interrupt sense control.
Bit 7:4 – Reserved
These bits are unused bits in the Atmel ATmega48PA/88PA/168PA, and will always read as zero.
Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The external interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set.
The level and edges on the external INT1 pin that activate the interrupt are defined in Table 13-1. The value on the INT1 pin
is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low
level must be held until the completion of the currently executing instruction to generate an interrupt.
Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The external interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set.
The level and edges on the external INT0 pin that activate the interrupt are defined in Table 13-2. The value on the INT0 pin
is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is selected, the low
level must be held until the completion of the currently executing instruction to generate an interrupt.
Bit
765
43210
–
ISC11
ISC10
ISC01
ISC00
EICRA
Read/Write
R
R/W
Initial Value
000
00000
Table 13-1. Interrupt 1 Sense Control
ISC11
ISC10
Description
0
The low level of INT1 generates an interrupt request.
0
1
Any logical change on INT1 generates an interrupt request.
1
0
The falling edge of INT1 generates an interrupt request.
1
The rising edge of INT1 generates an interrupt request.
Table 13-2. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
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