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參數(shù)資料
| 型號(hào)： | MB91F364GPMT |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 64 MHz, RISC MICROCONTROLLER, PQFP120 |
| 封裝： | PLASTIC, LQFP-120 |
| 文件頁(yè)數(shù)： | 117/239頁(yè) |
| 文件大小： | 3093K |
| 代理商： | MB91F364GPMT |
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MB91360G Series
203
(8) Notes to use of flash memory
Notes on the flash memory in MB91360G series devices are given below.
a : Input of hardware reset (INITX)
To input a hardware reset when the automatic algorithm is not started, where reading is in progress, a minimum
of 500 ns should be taken at a low-level width. In this case, a maximum of 500 ns is required until data can be
read from the flash memory after a hardware reset has been activated.
Similarly, to input a hardware reset when the automatic algorithm is activated, where writing/erasing is in
progress, a minimum of 50 ns should be taken in a low-level width. In this case, 20
s are required until data
can be read after the executing operation has been terminated to initialize the flash memory.
A hardware reset during writing undefined data being written. A hardware reset during erasing may make the
sector being erased unusable.
b : Canceling software reset, watchdog timer reset, and hardware standby
When writing/erasing the flash memory with the CPU access and if reset conditions occur while the automatic
algorithm is active, the CPU may run away. This occurs because these reset conditions cause the automatic
algorithm to continue without initializing the flash memory unit, possibly preventing the flash memory unit from
entering the read state when the CPU starts the sequence after the reset has been deasserted. These reset
conditions should be inhibited during writing/erasing the Flash Memory.
c : Program access to flash memory
When the automatic algorithm is operating, read access to the flash memory is disabled. With the memory
access mode of the CPU set to the internal ROM mode, writing/erasing should be started after switching the
program area to another area such as RAM.
In this case, when sectors containing interrupt vectors are erased, interrupt processing cannot be executed.
For the same reason, all interrupt sources should be disabled while the automatic algorithm is operating.
d : Hold function
When the CPU accepts a hold request, the Write signal WE of the flash memory unit may be skewed and many
cause erroneous writing/erasing. When the acceptance of a hold request is enabled, ensure that the WE bit of
the FLASH control status register (FMCS) is 0.
e : Applying VID
Applying VID required for the sector protect operation should always be started and terminated when the supply
voltage is on.
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| MB91F467DAPVSR-GSE2 | 32-BIT, FLASH, 100 MHz, RISC MICROCONTROLLER, PQFP208 |
| MB91F467PAPMC-GSE2 | RISC MICROCONTROLLER, PQFP176 |
| MB91F469GBPB-GS | 32-BIT, FLASH, 88 MHz, RISC MICROCONTROLLER, PBGA320 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MB91F365GBPMCR-GE1 | 制造商:FUJITSU 功能描述: |
| MB91F365GBPMCR-GSE1 | 制造商:FUJITSU 功能描述: |
| MB91F365GBPMT | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller |
| MB91F366GB | 制造商:FUJITSU 制造商全稱:Fujitsu Component Limited. 功能描述:32-bit RISC Microcontroller |
| MB91F366GBPMC3-G | 功能描述:MCU 32-BIT FR50 RISC 512KB FLASH RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:FR MB91360G 標(biāo)準(zhǔn)包裝:38 系列:Encore!® XP® 核心處理器:eZ8 芯體尺寸:8-位 速度:5MHz 連通性:IrDA，UART/USART 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，LED，POR，PWM，WDT 輸入/輸出數(shù):16 程序存儲(chǔ)器容量:4KB（4K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 3.6 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 105°C 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 包裝:管件 其它名稱:269-4116Z8F0413SH005EG-ND |
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