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MB91313A Series
18
DS07-16706-4E
■ HANDLING DEVICES
Preventing latch-up
Latch-up may occur in a CMOS IC if a voltage higher than VDDE or VDDI, or less than VSS is applied to an input
or output pin or if a voltage exceeding the rating is applied between VDDE and VSS, or VDDI and VSS. If
latch-up occurs, the power supply current increases rapidly, sometimes resulting in thermal breakdown of
the device. Therefore, be very careful not to apply voltages in excess of the absolute maximum ratings.
Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistance.
Power supply pins
In MB91313A series, devices including multiple of VDDE pins, VDDI pins and VSS pins are designed as follows;
pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latch-
up. All of the power supply pin and GND pin must be externally connected to the power supply and ground
respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground
level rising and to follow the total output current ratings. Furthermore, the VDDE pins, VDDI pins and VSS pins
of the MB91313A series must be connected to the current supply source via a low impedance. It is also
recommended to connect a ceramic capacitor of approximately 0.1
μF as a bypass capacitor between VDDE
pins, VDDI pins and VSS pins near this device.
Crystal oscillator circuit
Noise in proximity to the X0 and X1 (X0A, X1A) pins can cause the device to operate abnormally. Printed
circuit boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as
bypass capacitors connected to ground, are located near the device and ground.
It is recommended that the printed circuit board artwork be designed such that the X0 and X1 pins or X0A
and X1A pins are surrounded by ground plane for the stable operation.
Please request the oscillator manufacturer to evaluate the oscillational characteristics of the crystal and this
device.
Mode pins (MD0 to MD2)
When using mode pins, connect them directly to power supply pin or GND pin. To prevent the device from
entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin
and power supply pin or GND pin on the printed circuit board as possible and connect them with low
impedance.
Operation at power-on
Ensure that the INITX pin is reset and the settings are initialized (INIT) immediately after the power is turned
on.
Maintain the “L” level input to the INITX pin during the stabilization wait time immediately after the power on
to ensure the stabilization wait time as required by the oscillator circuit (the stabilization wait time is reset to
the minimum value when INIT is asserted using the INITX pin).
Note on oscillator input at power-on
At power-on, ensure that the clock is input until the oscillator stabilization wait time has elapsed.