參數(shù)資料
型號(hào)： MB89PV950CF
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 5 MHz, MICROCONTROLLER, CQFP64
封裝： 0.80 MM PITCH, PIGGY BACK, MQFP-64
文件頁(yè)數(shù)： 75/110頁(yè)
文件大小： 619K
代理商： MB89PV950CF
HARDWARE CONFIGURATION
2– 52
[Bit 4] SOE: Serial-data output-enable bit
This bit is used to control the output pin for serial I/O.
When using P43/SI pin as SI pin, always set the DDR4 to input (bit 3 of
DDR4 = 0).
This bit is valid when the RSEL bit of the SMC2 in the UART is 1.
[Bits 3 and 2] CKS1 and CKS0: Shift-clock select bits
These bits are used to select the serial shift-clock modes.
[Bit 1] BDS: Transfer direction select bit
At serial data transfer, this bit is used to decide the transfer direction: from
the least significant bit first (LSB first) or from the most significant bit first
(MSB first).
Note that when this bit is rewritten after writing data to the SDR, the data
become invalid.
[Bit 0] SST: Serial I/O transfer-start bit
This bit is used to start serial I/O transfer. The bit is automatically cleared
to 0 when transfer is terminated.
Before starting transfer, ensure that transfer is stopped (SST = 0).
Peripherals
General-purpose port pin (P44)
SO (serial data) output pin
0
1
SCK
0
1
0
1
Mode
0
1
Internal shift-clock mode
External shift-clock mode
CKS1
CKS0
Output
Input
(2 instruction cycle)
(8 instruction cycle)
(32 instruction cycle)
(SCK)
(Clock rate)
LSB first
MSB first
0
1
Stops serial I/O transfer
Starts serial I/O transfer
0
1
(b) Serial-data register (SDR)
This 8-bit register is used to hold serial I/O transfer data. (Note: Do not
write data to this register during the serial I/O operation.)
SMR
Address: 001CH
SDR
Address: 001DH
Address: 001DH
(Initial value)
XXXXXXXXB
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(R/W)
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