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參數(shù)資料
| 型號： | MAX9850 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Stereo Audio DAC with DirectDrive Headphone Amplifier |
| 中文描述： | 立體聲音頻DAC，帶有DirectDrive®耳機(jī)放大器 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大小： | 956K |
| 代理商： | MAX9850 |
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M
Least Significant Bit First (LSF)
1 = Accepts audio data LSB first.
0 = Accepts audio data MSB first.
Set LSF = 0 to conform to the I
2
S standard.
SDIN Delay (DLY)
1 = Audio data is latched into the MAX9850 on the sec-
ond rising BCLK edge after LRCLK transitions.
0 = Audio data is latched into the MAX9850 on the first
rising BCLK edge after LRCLK transitions.
Set DLY = 1 to conform to the I
2
S standard.
Right-Justified Data (RTJ)
1 = Audio data is right justified.
0 = Audio data is left justified.
I
2
S audio data is left justified. Set RTJ = 0 to conform to
the I
2
S standard.
Word Length Select (WS (1:0))
00 = Audio data word length is 16 bits.
01 = Audio data word length is 18 bits.
10 = Audio data word length is 20 bits.
11 = Audio data word length is 24 bits.
Program WS(1:0) to select the input data word length.
Programming the audio data word length ensures that
the correct number of BCLK cycles are output to
accommodate the incoming data word.
Digital Audio Interface
The MAX9850 receives serial digital audio data through
a 3-wire interface. The data can be right or left justified,
MSB or LSB first, or I
2
S compatible. The 3-wire serial
bus carries two time-multiplexed audio data channels
(SDIN), a channel-select line (LRCLK), and a bit clock
line (BCLK). The configuration of the audio interface is
controlled with the digital audio register, see Table 20.
Typical digital audio formats, and the required digital
audio register code, are listed in Table 21. Figure 4.
illustrates the difference between right justified, left jus-
tified, and I
2
S-compatible audio data.
Table 21. Typical Digital Audio Formats
The MAX9850 generates the BCLK and the LRCLK from
ICLK when in master mode, see the
Internal Timing
sec-
tion. In slave mode, the MAX9850 accepts an LRCLK and
BCLK from an external digital audio source.
The MAX9850 can accept right- or left-justified data when
operating in slave mode with extra BCLK pulses beyond
what is programmed by the WS(1:0) bits. When using the
I
2
S standard, audio data must latch into SDIN on the sec-
ond BCLK rising edge following an LRCLK transition. See
Figure 4 for the various relationships between clock and
data that are supported by the MAX9850.
The MAX9850 can be configured to accept 16, 18, 20,
or 24-bit data. The MAX9850 generates exactly the pro-
grammed number of BCLK cycles when in master
mode. Program the audio data word size with WS(1:0)
(register 0xA, bit B0 and B1) according to Table 22 to
ensure that the MAX9850 outputs the correct number of
BCLK cycles to accommodate the input word.
Table 22. Audio Data Word Size
The internal digital processing resolution is 18 bits
wide. Data words longer than 18 bits will be truncated.
Zeros are internally programmed into the missing bit
positions when the data word is shorter than the pro-
grammed word size.
I
2
C-Compatible Serial Interface
The MAX9850 features an I
2
C/SMBus-compatible, 2-
wire serial interface consisting of a serial data line
(SDA) and a serial clock line (SCL). SDA and SCL facili-
tate communication between the MAX9850 and the
master at clock rates up to 400kHz. Figure 5 shows the
2-wire interface timing diagram. The master generates
SCL and initiates data transfer on the bus.
A master device writes data to the MAX9850 by trans-
mitting the proper slave address followed by the regis-
ter address and then the data word. Each transmit
sequence is framed by a START (S) or REPEATED
START (S
r
) condition and a STOP (P) condition. Each
word transmitted to the MAX9850 is 8 bits long and is
followed by an acknowledge clock pulse.
Stereo Audio DAC with DirectDrive
Headphone Amplifier
28
______________________________________________________________________________________
FORMAT
DIGITAL AUDIO REGISTER
CODE (0xA)
Left-Justified Audio Data
Right-Justified Audio Data
I
2
S-Compatible Audio Data
X0000000
X0000100
X0001000
WS(1:0)
0x0
0x1
0x2
0x3
DATA WORD SIZE (BITS)
16
18
20
24
SMBus is a trademark of Intel Corp.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX98500EVKIT+ | 功能描述:音頻 IC 開發(fā)工具 MAX98500 Eval Kit RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類型:Audio Amplifiers 工具用于評估:TAS5614L 工作電源電壓:12 V to 38 V |
| MAX98500EWE+ | 制造商:Maxim Integrated Products 功能描述:BOOSTED CLASS D AMPLIFIER WITH ALC - Rail/Tube |
| MAX98500EWE+T | 功能描述:音頻放大器 2.2W Mono Class D Amplifier RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| MAX98502EVKIT# | 功能描述:放大器 IC 開發(fā)工具 MAX98502 Eval Kit RoHS:否 制造商:International Rectifier 產(chǎn)品:Demonstration Boards 類型:Power Amplifiers 工具用于評估:IR4302 工作電源電壓:13 V to 23 V |
| MAX98502EWE+ | 功能描述:音頻放大器 Boosted Class D Amplifier RoHS:否 制造商:STMicroelectronics 產(chǎn)品:General Purpose Audio Amplifiers 輸出類型:Digital 輸出功率: THD + 噪聲: 工作電源電壓:3.3 V 電源電流: 最大功率耗散: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
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