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參數(shù)資料
| 型號： | MAX9424 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Lowest Jitter Quad PECL-to-ECL Differential Translators |
| 中文描述： | 低抖動、四路PECL至ECL差分轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 353K |
| 代理商： | MAX9424 |
Synchronous Operation
Setting SEL = low and
SEL
= high enables all four
channels to operate in synchronous mode where the
buffered inputs are clocked out simultaneously on the
rising edge of the differential clock input (CLK and
CLK
). To have the input signals clocked out on the
falling edge, swap the clock lines.
Differential Signal Input
The maximum input signal magnitude for each of the
devices is V
CC
- V
GG
or 3.0V, whichever is less. This
includes IN_,
IN_
, CLK,
CLK
, SEL,
SEL
, EN and
EN
.
Applications Information
Input Bias
Bias any unused inputs as shown in Figure 5. This
avoids noise coupling that can cause toggling of the
unused outputs.
Output Termination
Terminate the open-emitter outputs (MAX9424/
MAX9426) through 50
to V
GG
- 2V or use equivalent
Thevenin terminations. Terminate both outputs of a dif-
ferential pair and use identical termination on each for
the lowest output-to-output skew. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if OUT0 is used as a single-
ended output, terminate both OUT0 and
OUT0
.
Ensure that output currents do not exceed the current
limits as specified in the
Absolute Maximum Ratings
.
Under all operating conditions, the device
’
s total ther-
mal limits should be observed.
Power-Supply Bypassing
Typically, V
GG
is directly connected to ground. Bypass
each V
CC
pin to V
GG
with high-frequency surface-mount
ceramic 0.01μF capacitors. Place these capacitors as
close to the device as possible. Use the same bypass
capacitor configuration between each V
EE
pin and V
GG
.
In high-frequency, high-noise environments, add a 0.1μF
capacitor in parallel with each 0.01μF capacitor.
Use multiple vias when connecting the bypass capaci-
tors to V
GG
(ground). This reduces trace inductance,
lowering power-supply bounce when drawing high
transient currents.
Circuit Board Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
Signal reflections are caused by discontinuities in the
50
characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners, and using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
Chip Information
TRANSISTOR COUNT: 882
PROCESS: Bipolar
M
Lowest Jitter Quad PECL-to-ECL
Differential Translators
_______________________________________________________________________________________
9
IN_
IN_
100
1k
V
CC
V
GG
1/4 MAX9424/MAX9425
OUT_
OUT_
IN_
IN_
1k
V
CC
V
GG
1/4 MAX9426/MAX9427
OUT_
OUT_
100
Figure 5. Input Bias Circuits for Unused Inputs
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