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參數(shù)資料
| 型號(hào)： | MAX9424 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Lowest Jitter Quad PECL-to-ECL Differential Translators |
| 中文描述： | 低抖動(dòng)、四路PECL至ECL差分轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 3/11頁(yè) |
| 文件大?。?/td> | 353K |
| 代理商： | MAX9424 |
M
Lowest Jitter Quad PECL-to-ECL
Differential Translators
_______________________________________________________________________________________
3
AC ELECTRICAL CHARACTERISTICS
(V
CC
- V
GG
= 2.375V to 5.5V, V
GG
- V
EE
= 2.375V to 5.5V, outputs terminated with 50
to V
GG
- 2.0V, EN = V
IHD
,
EN
= V
ILD
, f
CLK
≤
3.0GHz, f
IN
≤
1.5GHz, input transition time = 125ps (20% to 80%), V
IHD
= V
GG
+ 1.4V to V
CC
, V
ILD
= V
GG
to V
CC
- 0.2V, V
IHD
- V
ILD
= 0.2V to smallest of |V
CC
- V
GG
| or 3.0V, T
A
= -40
°
C to +85
°
C, unless otherwise noted. Typical values are at V
CC
- V
GG
= 3.3V, V
GG
- V
EE
= 3.3V, V
IHD
= V
CC
- 0.9V, V
ILD
= V
CC
- 1.7V, T
A
= +25
°
C, unless otherwise noted.) (Notes 1 and 5)
PARAMETER
SYMBOL
t
PLH1
t
PHL1
t
PLH2
t
PHL2
CONDITIONS
MIN
TYP
MAX
UNITS
IN_ to OUT_ Differential
Propagation Delay
CLK to OUT_ Differential
Propagation Delay
Figure 3, SEL = high, asynchronous
operation
300
420
570
ps
Figure 4, SEL = low, synchronous operation
460
580
730
ps
OUT_ to OUT_ Skew
t
SKD1
SEL = high, asynchronous operation
(Note 6)
SEL = low, synchronous operation (Note 6)
MAX9424/MAX9426, V
OH
- V
OL
≥
500mV,
SEL = low
MAX9425/MAX9427, V
OH
- V
OL
≥
300mV,
SEL = low
MAX9424/MAX9426, V
OH
- V
OL
≥
400mV,
SEL = high
MAX9425/MAX9427, V
OH
- V
OL
≥
250mV,
SEL = high
SEL = low, f
CLK
= 3.0GHz clock, f
IN
=
1.5GHz (Note 7)
SEL = high, f
IN
= 2.0GHz (Note 7)
SEL = low, f
CLK
= 3.0GHz, IN_ = 3.0Gbps
2
23
- 1 PRBS pattern (Note 7)
SEL = high, IN_ = 2.0Gbps 2
23
- 1 PRBS
pattern (Note 7)
Figure 4
Figure 4
Figure 3
Figure 3
38
90
ps
OUT_ to OUT_ Skew
t
SKD2
10
70
ps
Maximum Clock Frequency
f
CLK(MAX)
3.0
GHz
Maximum Data Frequency
f
IN(MAX)
2.0
GHz
0.24
0.8
Added Random Jitter
t
RJ
0.3
0.8
ps
(RMS)
27
80
Added Deterministic Jitter
t
DJ
20
80
ps
(P-P)
IN_ to CLK Setup Time
CLK to IN_ Hold Time
Output Rise Time
Output Fall Time
Propagation Delay Temperature
Coefficient
t
S
t
H
t
R
t
F
80
80
ps
ps
ps
ps
89
87
120
120
t
PD
/
T
0.2
1
ps/
°
C
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters are production tested at +25
°
C. DC limits are guaranteed by design and characterization over the full
operating temperature range.
Note 4:
All outputs open, all inputs biased differential high or low except V
CC
, V
GG
, and V
EE
.
Note 5:
Guaranteed by design and characterization, and are not production tested. Limits are set to ±6 sigma.
Note 6:
Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 7:
Device jitter added to the input signal.
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