參數(shù)資料
型號(hào): MAX9323
廠商: Maxim Integrated Products, Inc.
英文描述: One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver
中文描述: 1至4 LVCMOS至LVPECL輸出時(shí)鐘和數(shù)據(jù)驅(qū)動(dòng)器
文件頁(yè)數(shù): 6/9頁(yè)
文件大?。?/td> 173K
代理商: MAX9323
M
1:5 Clock Driver with Selectable
LVPECL Inputs and LVDS Outputs
6
_______________________________________________________________________________________
CLK
CLK
Q_
Q_
t
PLHD
t
PHLD
V
OH
- V
OL
V
IHD
- V
ILD
V
IHD
V
ILD
Q_ - Q_
0V (DIFFERENTIAL)
0V (DIFFERENTIAL)
20%
80%
20%
80%
t
R
t
F
V
OL
V
OH
Figure 1. MAX9310 Timing Diagram
t
S
t
H
t
S
t
PLHD
OUTPUTS ARE LOW
OUTPUTS STAY LOW
EN
CLK
CLK
Q_
Q_
t
H
t
S
= SETUP TIME
t
H
= HOLD TIME
Figure 2. MAX9310
EN
Timing Diagram
Pin Description (continued)
PIN
NAME
FUNCTION
18, 20
V
CC
Positive Supply Voltage. Bypass each V
CC
to GND with 0.1μF and 0.01μF ceramic capacitors.
Place the capacitors as close to the device as possible with the smaller value capacitor closest
to the device.
19
EN
Output Enable Input. Outputs are synchronously enabled on the falling edge of the selected
clock input when
EN
is low. Outputs are synchronously driven to a differential low state on the
falling edge of the selected clock input when
EN
is high. Internal 60k
pulldown to GND
(Figure 2).
相關(guān)PDF資料
PDF描述
MAX9324 One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
MAX9326 1:9 Differential LVPECL/LVECL/HSTL Clock and Data Driver
MAX9382EVKIT Evaluation Kit for the MAX9382/MAX9383
MAX9383 ECL/PECL Phase-Frequency Detectors
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