參數(shù)資料
型號: MAX9323
廠商: Maxim Integrated Products, Inc.
英文描述: One-to-Four LVCMOS-to-LVPECL Output Clock and Data Driver
中文描述: 1至4 LVCMOS至LVPECL輸出時(shí)鐘和數(shù)據(jù)驅(qū)動(dòng)器
文件頁數(shù): 4/9頁
文件大?。?/td> 173K
代理商: MAX9323
SUPPLY CURRENT vs. TEMPERATURE
M
TEMPERATURE (
°
C)
S
60
35
10
-15
41
42
43
44
45
46
47
48
49
50
40
-40
85
ALL PINS ARE OPEN EXCEPT V
AND GND OUTPUTS LOADED WITH 100
DIFFERENTIAL
DIFFERENTIAL OUTPUT VOLTAGE (V
OH
- V
OL
)
vs. FREQUENCY
450
M
FREQUENCY (GHz)
D
1.50
1.25
0.25
0.50
0.75
1.00
100
150
200
250
300
350
400
50
0
1.75
OUTPUT RISE/FALL vs. TEMPERATURE
M
TEMPERATURE (
°
C)
R
60
35
10
-15
205
210
215
220
200
-40
85
t
F
t
R
f
IN
= 500MHz
Typical Operating Characteristics
(V
CC
- GND = 2.5V, outputs terminated with 100
±
1%, f
IN
= 1.0GHz, input transition time = 125ps (20% to 80%),V
IHD
= V
CC
- 1.0V,
V
ILD
= V
CC
- 1.5V, unless otherwise noted.)
M
1:5 Clock Driver with Selectable
LVPECL Inputs and LVDS Outputs
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS (continued)
(V
CC
- GND = 2.375V to 2.625V, outputs terminated with 100
±
1%, f
IN
1.0GHz, input transition time = 125ps (20% to 80%),
V
IHD
- V
ILD
= 0.15V to V
CC
, unless otherwise noted. Typical values are at V
CC
- GND = 2.5V, V
IHD
= V
CC
- 1.0V, V
ILD
= V
CC
- 1.5V,
unless otherwise noted.) (Notes 1 and 5)
-40
°
C
TYP
+25
°
C
TYP
+85
°
C
TYP
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
Operating
Frequency
f
MAX
V
OD
250mV
1.0
1.0
1.0
GHz
Differential
Output Rise/Fall
Time
t
R/tF
20% to 80%,
Figure 1
140
205
300
140
205
300
140
205
300
ps
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters are production tested at +25
°
C. DC limits are guaranteed by design and
characterized over the full operating temperature range.
Note 4:
All pins are open except V
CC
and GND, all outputs are loaded with 100
differentially.
Note 5:
Guaranteed by design and characterization. Limits are set to ±6 sigma.
Note 6:
Measured between outputs of the same part at the signal crossing points for a same-edge
transition.
Note 7:
Measured between outputs of different parts at the signal crossing points under identical conditions
for a same-edge transition.
Note 8:
Device jitter added to the input signal.
相關(guān)PDF資料
PDF描述
MAX9324 One-to-Five LVPECL/LVCMOS Output Clock and Data Driver
MAX9325 2:8 Differential LVPECL/LVECL/HSTL Clock and Data Driver
MAX9326 1:9 Differential LVPECL/LVECL/HSTL Clock and Data Driver
MAX9382EVKIT Evaluation Kit for the MAX9382/MAX9383
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