![](http://datasheet.mmic.net.cn/370000/MAX9315_datasheet_16718708/MAX9315_7.png)
V
EE
connected to ground, the outputs are LVPECL. The
outputs are LVECL when V
CC
is connected to ground
and V
EE
is connected to a negative supply.
Input Bias Resistors
When the inputs are open, the internal bias resistors set
the inputs to low state. The inverting inputs (
CLK0
and
CLK1
) are each biased with a 75k
pullup to V
CC
and a
75k
pulldown to V
EE
. The noninverting inputs (CLK0
and CLK1) are each biased with a 75k
pulldown to V
EE
.
Differential Cloc k Input Limits
The maximum magnitude of the differential signal
applied to the clock input is 3.0V or V
CC
- V
EE
, whichev-
er is less. This limit also applies to the difference
between any reference voltage input and a single-ended
input. Specifications for the high and low voltages of a
differential input (V
IHD
and V
ILD
) and the differential input
voltage (V
IHD
- V
ILD
) apply simultaneously.
S ingle-Ended Cloc k Input and V
BB
The differential clock inputs can be configured to
accept single-ended inputs. This is accomplished by
connecting the on-chip reference voltage, V
BB
, to the
inverting or noninverting input of a differential input as a
reference. For example, the differential CLK0,
CLK0
input is converted to a noninverting, single-ended input
by connecting V
BB
to
CLK0
and connecting the single-
ended input signal to CLK0. Similarly, an inverting con-
figuration is obtained by connecting V
BB
to CLK0 and
connecting the single-ended input to
CLK0
. With a dif-
ferential input configured as single ended (using V
BB
),
the single-ended input can be driven to V
CC
and V
EE
or
with a single-ended LVPECL/LVECL signal. Note that
single-ended input must be at least V
BB
±100mV or a
differential input of at least 100mV to switch the outputs
to the V
OH
and V
OL
levels specified in the
DC Electrical
Characteristics
table.
If V
BB
is used, the supply must be in the V
CC
- V
EE
=
+2.725V to +3.8V range because one of the inputs
must be V
EE
+ 1.2V or higher for proper input stage
operation. V
BB
must be at least V
EE
+ 1.2V because it
becomes the high-level input when the other (single-
ended) input swings below it. Therefore, minimum V
BB
= V
EE
+ 1.2V. The minimum V
BB
output of the
MAX9315 is V
CC
- 1.525V. Substituting the minimum
V
BB
output into VBB= V
EE
+ 1.2V results in a minimum
supply of +2.725V. Rounding up to standard supplies
gives the single-ended operating supply range of V
CC
-
V
EE
= +3.0V to +3.8V.
When using the V
BB
reference output, bypass it with a
0.01μF ceramic capacitor to V
CC
. If the V
BB
reference
is not used, leave it open. The V
BB
reference can
source or sink 0.5mA, which is sufficient to drive two
inputs. Use V
BB
only for inputs that are on the same
device as the V
BB
reference.
Applic ations Information
S upply Bypassing
Bypass V
CC
to V
EE
with high-frequency surface-mount
ceramic 0.1μF and 0.01μF capacitors in parallel as
close to the device as possible, with the 0.01μF capaci-
tor closest to the device. Use multiple parallel vias to
minimize parasitic inductance. When using the V
BB
ref-
erence output, bypass it with a 0.01μF ceramic capaci-
tor to V
CC
(if the V
BB
reference is not used, it can be
left open).
Controlled-Impedanc e T rac es
Input and output trace characteristics affect the perfor-
mance of the MAX9315. Connect high-frequency input
and output signals with 50
characteristic impedance
traces. Minimize the number of vias to prevent imped-
ance discontinuities. Reduce reflections by maintaining
the 50
characteristic impedance through cables and
connectors. Reduce skew within a differential pair by
matching the electrical length of the traces.
Output T ermination
Terminate outputs with 50
to V
CC
- 2V or use an
equivalent Thevenin termination. When a single-ended
signal is taken from a differential output, terminate both
outputs. For example, if Q0 is used as a single-ended
output, terminate both Q0 and
Q0
.
Chip Information
TRANSISTOR COUNT: 616
PROCESS: Bipolar
M
1:5 Differential LV PECL/LV ECL/HS T L
Cloc k and Data Driver
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