參數(shù)資料
型號(hào): MAX9315
廠商: Maxim Integrated Products, Inc.
英文描述: 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
中文描述: 1:5差分LVPECL/LVECL/HSTL時(shí)鐘和數(shù)據(jù)驅(qū)動(dòng)器
文件頁(yè)數(shù): 4/11頁(yè)
文件大小: 125K
代理商: MAX9315
M
1:5 Differential LV PECL/LV ECL/HS T L
Cloc k and Data Driver
4
_______________________________________________________________________________________
AC ELECTRICAL CHARACTERISTICS
(V
CC
- V
EE
= 2.375V to 3.8V, outputs loaded with 50
±1% to V
CC
- 2V, input frequency = 1.5GHz, input transition time = 125ps (20%
to 80%), SEL = high or low,
EN
= low, V
IHD
= V
EE
+ 1.2V to V
CC
, V
ILD
= V
EE
to V
CC
- 0.15V, V
IHD
- V
ILD
= 0.15V to the smaller of 3V or
V
CC
- V
EE
, unless otherwise noted. Typical values are at V
CC
- V
EE
= +3.3V, V
IHD
= V
CC
- 1V, V
ILD
= V
CC
- 1.5V.) (Notes 1, 7)
-40
°
C
+25
°
C
+85
°
C
UNITS
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
ps
Differential Input-
to-Output Delay
t
PLHD
,
t
PHLD
Figure 2
290
400
310
440
300
520
ps
Output-to-Output
Skew (Note 8)
t
SKOO
5
30
20
40
20
50
ps
Part-to-Part Skew
(Note 9)
t
SKPP
110
130
220
ps
Added Random
J itter (Note 10)
t
RJ
f
IN
= 1.5GHz clock
0.8
1.2
0.8
1.2
0.8
1.2
p s
( RM S
Added
Deterministic J itter
(Note 10)
t
DJ
1.5Gbps 2E
23
-1
PRBS pattern
50
70
50
70
50
70
ps (p-p)
Switching
Frequency
f
MAX
(V
OH
- V
OL
)
400mV,
Figure 2
1.5
1.5
1.5
GHz
Output Rise/Fall
Time (20% to 80%)
t
R
, t
F
Figure 2
80
120
90
130
90
145
ps
Note 1:
Measurements are made with the device in thermal equilibrium.
Note 2:
Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3:
DC parameters production tested at T
A
= +25°C and guaranteed by design over the full operating temperature range.
Note 4:
Single-ended input operation using V
BB
is limited to V
CC
- V
EE
= 3.0V to 3.8V.
Note 5:
Use V
BB
only for inputs that are on the same device as the V
BB
reference.
Note 6:
All pins open except V
CC
and V
EE
.
Note 7:
Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8:
Measured between outputs of the same part at the signal crossing points for a same-edge transition.
Note 9:
Measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition.
Note 10:
Device jitter added to the input signal.
相關(guān)PDF資料
PDF描述
MAX9315EUP 1:5 Differential LVPECL/LVECL/HSTL Clock and Data Driver
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