參數(shù)資料
型號(hào)： MAX9273GTL+T
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 3/49頁(yè)
文件大?。?/td> 0K
描述： IC SERIALIZER 22BIT GMSL 40TQFN
標(biāo)準(zhǔn)包裝： 2,500
系列： *
MAX9273
22-Bit GMSL Serializer with Coax or
STP Cable Drive
11
Maxim Integrated
Pin Description
Pin Configuration
PIN
NAME
FUNCTION
1, 2, 3, 5–8,
16, 17, 32,
33, 34, 36,
37, 38
DIN0–DIN13,
DIN20, DIN21
Parallel Data Inputs with Internal Pulldown to EP
4, 27
AVDD
1.8V Analog Power Supply. Bypass AVDD to EP with 0.1FF and 0.001FF capacitors as close
as possible to the device with the smaller capacitor closest to AVDD.
9–12
DIN14/
GPIO2–DIN17/
GPIO5
Parallel Data Inputs/GPIO. Defaults to parallel data input on power-up.
Parallel data input has internal pulldown to EP.
GPIO_ has an open-drain output with internal 60kI pullup to IOVDD. See register table
for programming details.
13
DIN18/HS
Parallel Data Input/Horizontal Sync with Internal Pulldown to EP. Defaults to parallel data input
on power-up.
Horizontal sync input when VS/HS encoding is enabled (Table 2).
14
DIN19/VS
Parallel Data Input/Vertical Sync with Internal Pulldown to EP. Defaults to parallel data input on
power-up.
Vertical sync input when VS/HS encoding is enabled (Table 2).
TQFN
(6mm x 6mm x 0.75mm)
CONNECT EP TO GROUND PLANE
MAX9273
TOP VIEW
35
36
34
33
12
11
13
DIN8
AVDD
DIN10
DIN11
DIN12
14
DIN7
AVDD
OUT-
CONF1
RX
/SDA
TX
/SCL
CONF0
DRS
12
DIN2
45
67
27
28
29
30
26
24 23 22
DVDD
DIN3
GPO
DIN21
DIN20
IOVDD
DIN9
OUT+
3
25
37
DIN4
DIN19/VS
38
39
40
DIN5
IOVDD
EP*
DIN6
DIN18/VS
DIN17/GPIO5
DIN16/GPIO4
+
DIN1
32
15
GPIO1
DIN0
31
16
17
18
19
20 MS
DIN13
DIN14/
GPIO2
DIN15/
GPIO3
89
10
21
PCLKIN
AUTOS
PWDN
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