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參數(shù)資料
| 型號： | MAX9217ETM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 27-Bit, 3MHz-to-35MHz DC-Balanced LVDS Serializer |
| 中文描述： | LINE DRIVER, QCC48 |
| 封裝： | 6 X 6 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, QFN-48 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大小： | 230K |
| 代理商： | MAX9217ETM |
M
27-Bit, 3MHz-to-35MHz
DC-Balanced LVDS Serializer
_______________________________________________________________________________________
5
Pin Description
PIN
NAME
GND
FUNCTION
1, 13, 37
Input Buffer Supply and Digital Supply Ground
2
V
CCIN
Input Buffer Supply Voltage. Bypass to GND with 0.1μF and 0.001μF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
3
–
10,
39
–
48
RGB_IN[17:0]
LVTTL/LVCMOS Red, Green, and Blue Digital Video Data Inputs. Eighteen data bits are loaded
into the input latch on the rising edge of PCLK_IN when DE_IN is high. Internally pulled down to
GND.
11, 12, 15
–
21
CNTL_IN[8:0]
LVTTL/LVCMOS Control Data Inputs. Control data are latched on the rising edge of PCLK_IN
when DE_IN is low. Internally pulled down to GND.
14, 38
V
CC
Digital Supply Voltage. Bypass to GND with 0.1μF and 0.001μF capacitors in parallel as close to
the device as possible, with the smallest value capacitor closest to the supply pin.
22
DE_IN
LVTTL/LVCMOS Data Enable Input. Logic-high selects RGB_IN[17:0] to be latched. Logic-low
selects CNTL_IN[8:0] to be latched. DE_IN must be switching for proper operation. Internally
pulled down to GND.
23
PCLK_IN
LVTTL/LVCMOS Parallel Clock Input. Latches data and control inputs and provides the PLL
reference clock. Internally pulled down to GND.
24
MOD0
LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled
down to GND.
25
MOD1
LVTTL/LVCMOS Modulation Rate Input. Selects the phase-modulation step size. Internally pulled
down to GND.
26
PLL GND
PLL Supply Ground
27
V
CCPLL
PLL Supply Voltage. Bypass to PLL GND with 0.1μF and 0.001μF capacitors in parallel as close
to the device as possible, with the smallest value capacitor closest to the supply pin.
28
PWRDWN
LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND.
29
CMF
Common-Mode Filter. Optionally connect a capacitor between CMF and ground to filter
common-mode switching noise.
30, 31
32
33
LVDS GND
OUT-
OUT+
LVDS Supply Ground
Inverting LVDS Serial Data Output
Noninverting LVDS Serial Data Output
34
V
CCLVDS
LVDS Supply Voltage. Bypass to LVDS GND with 0.1μF and 0.001μF capacitors in parallel as
close to the device as possible, with the smallest value capacitor closest to the supply pin.
35
RNG1
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
36
RNG0
LVTTL/LVCMOS Frequency Range Select Input. Set to the frequency range that includes the
PCLK_IN frequency as shown in Table 3. Internally pulled down to GND.
EP
GND
Exposed Pad (Thin QFN Package Only). Connect Thin QFN exposed pad to PC board GND.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9217ETM+ | 功能描述:串行器/解串器 - Serdes 27-Bit DC-Balanced Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9217ETM+T | 功能描述:串行器/解串器 - Serdes 27-Bit DC-Balanced Serializer RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| MAX9217ETM+T&R | 制造商:Maxim Integrated Products 功能描述:27-BIT, 3MHZ-TO-35MHZ DC-BALANCED LVDS SERIALIZER - Tape and Reel |
| MAX9217ETM-T | 制造商:Maxim Integrated Products 功能描述:27-BIT 3MHZ-TO-35MHZ DC-BALANCED LVDS SERIALI - Tape and Reel |
| MAX9217EVKIT+ | 功能描述:界面開發(fā)工具 MAX9217/18 Eval Kit RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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