- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄385554 > MAX9158 (Maxim Integrated Products, Inc.) Quad Bus LVDS Transceiver in 44 QFN PDF資料下載
參數(shù)資料
| 型號： | MAX9158 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Quad Bus LVDS Transceiver in 44 QFN |
| 中文描述： | 四路、總線式LVDS收發(fā)器，44 QFN封裝 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 358K |
| 代理商： | MAX9158 |
a driver located on a card in the middle of the bus is
27
because the driver sees two 54
loads in parallel.
A typical LVDS driver (rated for a 100
load) would not
develop a large enough differential signal to be reliably
detected by an LVDS receiver. The MAX9158 BLVDS
drivers are designed and specified to drive a 27
load
to differential voltage levels of 250mV to 460mV. A stan-
dard LVDS receiver is able to detect this level of differ-
ential signal. Short extensions off the bus, called stubs,
contribute to capacitive loading. Keep stubs less than
1in for a good balance between ease of component
placement and good signal integrity.
The MAX9158 driver outputs are current-source drivers
and drive larger differential signal levels into loads
lighter than 27
and smaller levels into loads heavier
than 27
(see
Typical Operating Characteristics
curves). To keep loading from reducing bus impedance
below the rated 27
load, PC board traces can be
designed for higher unloaded characteristic impedance.
Effect of Transition Times
For transition times (measured from 0% to 100%) short-
er than the delay between capacitive loads, the loads
are seen as low-impedance discontinuities from which
the driven signal is reflected. Reflections add and sub-
tract from the signal being driven, causing jitter and
decreased noise margin. The MAX9158 output drivers
are designed for a minimum transition time of 1ns
(rated 0.6ns from 20% to 80%, or 1ns from 0% to
100%) to reduce reflections while being fast enough for
high-speed backplane data transmission.
Power-On Reset
The power-on reset voltage of the MAX9158 is typically
2.25V. When the supply falls below this voltage, the
devices are disabled and the receiver inputs/driver out-
puts are in high impedance. The power-on reset
ensures glitch-free power-up and power-down, allow-
ing hot swapping of cards in a multicard bus system
without disrupting communications.
Operating Modes
The MAX9158 features driver/receiver enable inputs
that select the bus I/O function (Table 1). Tables 2 and
3 show the driver and receiver operating modes.
Input Internal Pullup/Pulldown
Resistors
The MAX9158 includes pullup or pulldown resistors
(300k
) to ensure that unconnected inputs are defined
(Table 4).
Applications Information
Supply Bypassing
Bypass each supply pin with high-frequency surface-
mount ceramic 0.1μF and 1nF capacitors in parallel as
close to the device as possible, with the smaller value
capacitor closest to the device.
Termination
In the example given in the
Effect of Capacitive Loading
section, the loaded differential impedance of a bus is
reduced to 54
. Since the bus can be driven from any
card position, the bus must be terminated at each end.
A parallel termination of 54
at each end of the bus
placed across the traces that make up the differential
pair provides a proper termination. The total load seen
by the driver is 27
. The MAX9158 drives higher differ-
ential signal levels into lighter loads. (See the Differential
Output Voltage vs. Output Load graph in the
Typical
Operating Characteristics
section.) A multidrop bus with
the driver at one end and receivers connected at regu-
lar intervals along the bus has a lowered impedance
due to capacitive loading. Assuming a 54
impedance,
the multidrop bus can be terminated with a single, par-
allel-connected 54
resistor at the far end from the dri-
ver. Only a single resistor is required because the driver
sees one 54
differential trace. The signal swing is larg-
er with a 54
load. In general, parallel terminate each
end of the bus with a resistor matching the differential
impedance of the bus (taking into account any reduced
impedance due to loading).
M
Quad Bus LVDS Transceiver in 44 QFN
_______________________________________________________________________________________
9
MODE SELECTED
Driver Mode
Receiver Mode
High-Impedance Mode
Loopback Mode
DE_
H
L
L
H
RE_
H
L
H
L
Table 1. I/O Enable Functional Table
INPUTS
OUTPUTS
DE_
H
H
L
DIN_
L
H
X
DO_+/RIN_+
L
H
Z
DO_-/RIN_-
H
L
Z
Table 2. Driver Mode
相關PDF資料 |
PDF描述 |
|---|---|
| MAX9159 | Dual LVDS Line Receiver |
| MAX9159ESA | Dual LVDS Line Receiver |
| MAX9173ESE | Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe |
| MAX9173ETE | Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe |
| MAX9173EUE | Quad LVDS Line Receiver with Flow-Through Pinout and “In-Path” Fail-Safe |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX9158EGM | 制造商:Maxim Integrated Products 功能描述:QUAD BUS LVDS TRANSCEIVER IN 44-PIN QFN - Rail/Tube 制造商:Rochester Electronics LLC 功能描述: |
| MAX9158EGM-T | 制造商:Maxim Integrated Products 功能描述:QUAD BUS LVDS TRANSCEIVER IN 44-PIN QFN - Tape and Reel |
| MAX9159 | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Dual LVDS Line Receiver |
| MAX9159ESA | 制造商:Maxim Integrated Products 功能描述:DUAL LVDS LINE RECEIVER - Rail/Tube |
| MAX915C/D | 制造商:MAXIM 制造商全稱:Maxim Integrated Products 功能描述:Analog Comparator |
發(fā)布緊急采購，3分鐘左右您將得到回復。