參數(shù)資料
型號: MAX8588
廠商: Maxim Integrated Products, Inc.
英文描述: 8-Line To 1-Line Data Selectors/Multiplexers 20-LCCC -55 to 125
中文描述: 高效率、低IQ PMIC,帶有動態(tài)內(nèi)核,用于PDA和智能電話
文件頁數(shù): 5/31頁
文件大?。?/td> 572K
代理商: MAX8588
M
High-Efficiency, Low-I
Q
PMIC with
Dynamic Core for PDAs and Smartphones
_______________________________________________________________________________________
5
PARAMETER
CONDITIONS
LBI = IN (for preset)
With resistors at LBI
DBI = IN (for preset)
With resistors at LBI
MIN
3.51
0.98
3.024
1.208
2.25
61
-50
TYP
3.6
1.00
3.15
1.232
2.41
65.5
-5
15
+160
15
MAX
3.69
1.02
3.276
1.256
2.56
70
UNITS
LBI Threshold (Falling)
Hysteresis is 5% (typ)
V
DBI Threshold (Falling)
Hysteresis is 5% (typ)
V
RSO
Threshold (Falling)
RSO
Deassert Delay
LBI Input Bias Current
DBI Input Bias Current
Thermal-Shutdown Temperature
Thermal-Shutdown Hysteresis
LOGIC INPUTS AND OUTPUTS
Voltage on REG7, hysteresis is 5% (typ)
V
ms
nA
nA
°C
°C
50
T
J
rising
LBO
,
DBO
, POK,
RSO
, SDA Output
Low Level
2.6V
V7
5.5V, sinking 1mA
0.4
V
LBO
,
DBO
, POK,
RSO
Output Low
Level
V7
= 1V, sinking 100μA
0.4
V
LBO
,
DBO
, POK,
RSO
Output-High
Leakage Current
Pin
= 5.5V
0.2
μA
ON_, SCL, SDA,
SLP
, PWM3,
MR
,
SRAD Input High Level
2.6V
V
IN
5.5V
1.6
V
ON_, SCL, SDA,
SLP
, PWM3,
MR
,
SRAD Input Low Level
2.6V
V
IN
5.5V
0.4
V
ON_, SCL, SDA,
SLP
, PWM3,
MR
,
SRAD Input Leakage Current
Pin = GND, 5.5V
-1
+1
μA
SERIAL INTERFACE
Clock Frequency
400
kHz
Bus Free Time Between START and
STOP
1.3
μs
H ol d Ti m e Rep eated S TART C ond i on
CLK Low Period
CLK High Period
S etup Ti m e Rep eated S TART C ond i on
DATA Hold Time
DATA Setup Time
0.6
1.3
0.6
0.6
0
100
μs
μs
μs
μs
μs
ns
Maximum Pulse Width of Spikes that
Must be Suppressed by the Input
Filter of Both DATA and CLK Signals
50
ns
Setup Time for STOP Condition
0.6
μs
ELECTRICAL CHARACTERISTICS (continued)
(V
IN
= 3.6V, V
BKBT
= 3.0V, V
LBI
= 1.1V, V
DBI
= 1.35V, circuit of Figure 5,
T
A
= 0°C to +85°C
, unless otherwise noted. Typical values
are at T
A
= +25
°
C.)
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