M
_______________Detailed Desc ription
Reset Output
A microprocessor’s (μP’s) reset input starts the μP in a
known state. These μP supervisory circuits assert reset to
prevent code execution errors during power-up, power-
down, brownout conditions, or a watchdog timeout.
–————– is guaranteed to be a logic low for 0V < V
<
RST
, provided that VBATT is greater than 1V. Without
V
CC
exceeds the reset threshold, an
> 1V. Once V
period; after this interval,–————– goes high (Figure 2).
CC
dips below the
If a brownout condition occurs (V
is asserted, it stays low for the reset timeout period.
Any time V
goes below the reset threshold, the
internal timer restarts.
The watchdog timer can also initiate a reset. See the
Watchdog Inputsection.
The MAX804_/MAX805_ active-high RESET output is
open drain, and the inverse of the MAX690_/MAX704_/
Reset T hreshold
The MAX690T/MAX704T/MAX805T are intended for
3.3V systems with a ±5% power-supply tolerance and a
10% system tolerance. Except for watchdog faults,
reset will not assert as long as the power supply
remains above 3.15V (3.3V - 5%). Reset is guaranteed
to assert before the power supply falls below 3.0V.
The MAX690S/MAX704S/MAX805S are designed for
3.3V ±10% power supplies. Except for watchdog
faults, they are guaranteed not to assert reset as long
as the supply remains above 3.0V (3.3V - 10%). Reset
is guaranteed to assert before the power supply falls
below 2.85V (V
CC
- 14%).
The MAX690R/MAX704R/MAX805R are optimized for
monitoring 3.0V ±10% power supplies. Reset will not
occur until V
falls below 2.7V (3.0V - 10%), but is
guaranteed to occur before the supply falls below
2.59V (3.0V - 14%).
The MAX802R/S/T, MAX804R/S/T, and MAX806R/S/T
are respectively similar to the MAX690R/S/T,
MAX805R/S/T, and MAX704R/S/T, but with tightened
reset and power-fail threshold tolerances.
3.0V /3.3V Mic roproc essor S upervisory Circ uits
6
_______________________________________________________________________________________
______________________________________________________________Pin Desc ription
PIN
MAX804
MAX805
MAX806
1
V
OUT
Supply Output for CMOS RAM. When V
CC
is above the reset threshold, V
OUT
is
connected to V
CC
through a P-channel MOSFET switch. When V
CC
falls below V
SW
and
VBATT, VBATT connects to V
OUT
. Connect to V
CC
if no battery is used.
Main Supply Input
Ground
PFT
or when V
CC
falls below V
SW
, –——Ogoes
Power-Fail Input. When PFI is less than V
PFT
, or V
CC
falls below V
SW
, –——Ogoes low;
Power-Fail Output. When PFI is less than V
2
3
V
CC
GND
4
PFI
7
–————
Activis below the reset threshold or when –M—–is a logic low. It remains low for 200ms after
V
CC
either V
CC
rises above the reset threshold, the watchdog triggers a reset, or –M—–goes
from low to high.
Active-High, Open-Drain Reset Output is the inverse of –————–.
—
–M—–
Manual Reset Input. A logic low on –M—–asserts reset. Reset remains asserted as long as
–M—–is low and for 200ms after –M—–returns high. This active-low input has an internal
70μA pull-up current. It can be driven from a TTL or CMOS logic line, or shorted to
ground with a switch. Leave open if unused.
6
WDI
Watchdog Input. If WDI remains high or low for 1.6sec, the internal watchdog timer runs out
and reset is triggered. The internal watchdog timer clears while reset is asserted or when
WDI sees a rising or falling edge. The watchdog function cannot be disabled.
5
–——O
8
VBATT
Backup-Battery Input. When V
CC
falls below V
SW
and VBATT, V
OUT
switches from V
CC
to
VBATT. When V
CC
rises above the reset threshold, V
OUT
reconnects to V
CC
. VBATT may
exceed V
CC
. Connect to V
CC
if no battery is used.
—
RESET
NAME
FUNCTION
MAX690
MAX802
1
2
3
4
—
—
6
5
8
7
1
2
3
4
7
6
—
5
8
—
MAX704