參數(shù)資料
型號(hào): MAX7000S
廠商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可編程邏輯器件系列
文件頁數(shù): 49/62頁
文件大小: 1173K
代理商: MAX7000S
Altera Corporation
49
MAX 7000 Programmable Logic Device Family Data Sheet
Table 35. EPM7256S Internal Timing Parameters
Note (1)
Symbol
Parameter
Conditions
Speed Grade
Unit
-7
-10
-15
Min
Max
Min
Max
Min
Max
t
IN
t
IO
t
FIN
t
SEXP
t
PEXP
t
LAD
t
LAC
t
IOE
t
OD1
t
OD2
t
OD3
t
ZX1
t
ZX2
t
ZX3
t
XZ
t
SU
t
H
t
FSU
Input pad and buffer delay
0.3
0.5
2.0
ns
I/O input pad and buffer delay
0.3
0.5
2.0
ns
Fast input delay
3.4
1.0
2.0
ns
Shared expander delay
3.9
5.0
8.0
ns
Parallel expander delay
1.1
0.8
1.0
ns
Logic array delay
2.6
5.0
6.0
ns
Logic control array delay
2.6
5.0
6.0
ns
Internal output enable delay
0.8
2.0
3.0
ns
Output buffer and pad delay
C1 = 35 pF
0.5
1.5
4.0
ns
Output buffer and pad delay
C1 = 35 pF
(6)
1.0
2.0
5.0
ns
Output buffer and pad delay
C1 = 35 pF
5.5
5.5
8.0
ns
Output buffer enable delay
C1 = 35 pF
4.0
5.0
6.0
ns
Output buffer enable delay
C1 = 35 pF
(6)
4.5
5.5
7.0
ns
Output buffer enable delay
C1 = 35 pF
9.0
9.0
10.0
ns
Output buffer disable delay
C1 = 5 pF
4.0
5.0
6.0
ns
Register setup time
1.1
2.0
4.0
ns
Register hold time
1.6
3.0
4.0
ns
Register setup time of fast
input
2.4
3.0
2.0
ns
t
FH
Register hold time of fast
input
0.6
0.5
1.0
ns
t
RD
t
COMB
t
IC
t
EN
t
GLOB
t
PRE
t
CLR
t
PIA
t
LPA
Register delay
1.1
2.0
1.0
ns
Combinatorial delay
1.1
2.0
1.0
ns
Array clock delay
2.9
5.0
6.0
ns
Register enable time
2.6
5.0
6.0
ns
Global control delay
2.8
1.0
1.0
ns
Register preset time
2.7
3.0
4.0
ns
Register clear time
2.7
3.0
4.0
ns
PIA delay
(7)
3.0
1.0
2.0
ns
Low-power adder
(8)
10.0
11.0
13.0
ns
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