參數(shù)資料
型號: MAX7000S
廠商: Altera Corporation
英文描述: Programmable Logic Device Family
中文描述: 可編程邏輯器件系列
文件頁數(shù): 28/62頁
文件大?。?/td> 1173K
代理商: MAX7000S
28
Altera Corporation
MAX 7000 Programmable Logic Device Family Data Sheet
Tables 16
through
23
show the MAX 7000 and MAX 7000E AC operating
conditions.
Table 16. MAX 7000 & MAX 7000E External Timing Parameters
Note (1)
Symbol
Parameter
Conditions
-6 Speed Grade
-7 Speed Grade
Unit
Min
Max
Min
Max
t
PD1
t
PD2
t
SU
t
H
t
FSU
t
FH
t
CO1
t
CH
t
CL
t
ASU
t
AH
t
ACO1
t
ACH
t
ACL
t
CPPW
Input to non-registered output
C1 = 35 pF
6.0
7.5
ns
I/O input to non-registered output
C1 = 35 pF
6.0
7.5
ns
Global clock setup time
5.0
6.0
ns
Global clock hold time
0.0
0.0
ns
Global clock setup time of fast input
(2)
2.5
3.0
ns
Global clock hold time of fast input
(2)
0.5
0.5
ns
Global clock to output delay
C1 = 35 pF
4.0
4.5
ns
Global clock high time
2.5
3.0
ns
Global clock low time
2.5
3.0
ns
Array clock setup time
2.5
3.0
ns
Array clock hold time
2.0
2.0
ns
Array clock to output delay
C1 = 35 pF
6.5
7.5
ns
Array clock high time
3.0
3.0
ns
Array clock low time
3.0
3.0
ns
Minimum pulse width for clear and
preset
(3)
3.0
3.0
ns
t
ODH
t
CNT
f
CNT
Output data hold time after clock
C1 = 35 pF
(4)
1.0
1.0
ns
Minimum global clock period
6.6
8.0
ns
Maximum internal global clock
frequency
(5)
151.5
125.0
MHz
t
ACNT
f
ACNT
Minimum array clock period
6.6
8.0
ns
Maximum internal array clock
frequency
(5)
151.5
125.0
MHz
f
MAX
Maximum clock frequency
(6)
200
166.7
MHz
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