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      參數(shù)資料
      型號: MAX5965AEAX+
      廠商: Maxim Integrated
      文件頁數(shù): 7/54頁
      文件大小: 1334K
      描述: IC PSE CTRLR FOR POE 36SSOP
      產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
      Obsolescence Mitigation Program
      標準包裝: 30
      類型: 以太網(wǎng)供電控制器(PoE)
      應用: IP 電話,LAN 網(wǎng)絡(luò)供電,網(wǎng)絡(luò)路由器和交換機
      內(nèi)部開關(guān):
      電源電壓: 2.4 V ~ 3.6 V
      工作溫度: -40°C ~ 85°C
      安裝類型: 表面貼裝
      封裝/外殼: 36-BSOP(0.295",7.50mm 寬)
      供應商設(shè)備封裝: 36-SSOP
      包裝: 管件
      High-Power, Quad, Monolithic, PSE Controllers
      for Power over Ethernet
      _______________________________________________________________________________________   7
      ELECTRICAL CHARACTERISTICS (continued)
      (V
      AGND
      = 32V to 60V, V
      EE
      = 0V, V
      DD
      to V
      DGND
      = +3.3V, all voltages are referenced to V
      EE
      , unless otherwise noted. Typical values are at
      V
      AGND
      = +48V, V
      DGND
      = +48V, V
      DD
      = (V
      DGND
      + 3.3V), T
      A
      = +25癈. Currents are positive when entering the pin and negative other-
      wise.) (Note 2)
      PARAMETER
      SYMBOL
      CONDITIONS
      MIN
      TYP
      MAX
      UNITS
      Differential Nonlinearity
      DNL
      0.2
      1.5
      LSB
      Gain Error
      3
      %
      ADC Absolute Accuracy
      V
      SENSE_
       = 300mV
      295
      300
      305
      LSB
      TIMING CHARACTERISTICS (For 2-Wire Fast Mode)
      Serial-Clock Frequency
      f
      SCL
      400
      kHz
      Bus Free Time Between a
      STOP and START Condition
      t
      BUF
      1.2
      Hold Time for a START
      Condition
      t
      HD STA
      0.6
      Low Period of the SCL Clock
      t
      LOW
      1.2
      High Period of the SCL Clock
      t
      HIGH
      0.6
      Setup Time for a Repeated
      START Condition
      t
      SU STA
      0.6
      Data Hold Time
      t
      HD DAT
      100
      300
      ns
      Data in Setup Time
      t
      SU DAT
      100
      ns
      Rise Time of Both SDA and
      SCL Signals, Receiving
      t
      R
      20 +
      0.1C
      B
      300
      ns
      Fall Time of SDA Transmitting
      t
      F
      20 +
      0.1C
      B
      300
      ns
      Setup Time for STOP Condition
      t
      SU STO
      0.6
      Capacitive Load for Each Bus
      Line
      C
      B
      400
      pF
      Pulse Width of Spike
      Suppressed
      t
      SP
      50
      ns
      Note 2:   Limits to T
      A
      = -40癈 are guaranteed by design.
      Note 3:   Default values. The charge/discharge currents are programmable through the serial interface (see the Register Map and
      Description section).
      Note 4:   Default values. The current-limit thresholds are programmed through the I
      2
      C-compatible serial interface (see the Register
      Map and Description section).
      Note 5:   Functional test is performed over thermal shutdown entering test mode.
      Note 6:   This is the default value. Threshold can be programmed through serial interface R23h[2:0].
      Note 7:   AC disconnect works only if (V
      DD
      - V
      DGND
      ) e 3V and DGND is connected to AGND.
      Note 8:   t
      DISC
      can also be programmed through the serial interface (R16h) (see the Register Map and Description section).
      Note 9:   R
      D
      = (V
      OUT2
      - V
      OUT1
      )/(I
      DET2
      - I
      DET1
      ). V
      OUT1
      , V
      OUT2
      , I
      DET2
      , and I
      DET1
      represent the voltage at OUT_ and the current at
      DET_ during phase 1 and 2 of the detection.
      Note 10: Default values. The startup and fault times can also be programmed through the I
      2
      C serial interface (see the Register Map
      and Description section).
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