Quad PCI Express, Hot-Plug Controllers
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External MOSFET Gate Drivers
(12G_ and 3.3G_)
The gate drive for the external MOSFETs is provided at
12GA, 12GB, 12GC, 12GD, 3.3GA, 3.3GB, 3.3GC, and
3.3GD. 12G_ is the gate drive for the 12V main supply
and is boosted to 5.3V above V
12VIN
by its internal
charge pump. During turn-on, 12G_ sources 5礎(chǔ) into
the external gate capacitance to control the turn-on
time of the external MOSFET. During turn-off, 12G_
sinks 150礎(chǔ) from the external gate capacitance to
quickly turn off the external MOSFET. During short-cir-
cuit events, an internal 120mA current sink activates to
rapidly bring the load current into the regulation limits.
3.3G_ is the gate drive for the 3.3V main supplys MOS-
FET and is driven to 5.5V above the 3.3V main supply.
The power for 3.3G_ is supplied from 12VIN and has no
internal charge pump. During turn-on, 3.3G_ sources
5礎(chǔ) into the external gate capacitance to control the
turn-on time of the external MOSFET. During turn-off,
3.3G_ sinks 150礎(chǔ) to quickly turn off the external MOS-
FET. During short-circuit events, an internal 120mA cur-
rent sink activates to rapidly turn off the appropriate
external MOSFET.
Auxiliary Supply (3.3VAUXIN)
3.3VAUXIN provides power to the auxiliary outputs as
well as the internal logic and references. The drains of
the internal auxiliary MOSFETs connect to 3.3AUXIN
through internal sense resistors and the sources con-
nect to the auxiliary outputs (3.3VAUXO_). Both
MOSFETs have typical on-resistance of 0.2? Each
channels internal charge pump boosts the gate-drive
voltage to fully turn on the internal n-channel MOSFETs.
The auxiliary supplies have an internal current limit set
to 450mA (MAX5959) or 700mA (MAX5960).
Applications Information
Setting the Power-On Reset
t
FAULT
is the time an overcurrent or overtemperature
fault must remain for the MAX5959/MAX5960 to disable
the main or auxiliary channels of a particular slot.
Program the fault timeout period (t
FAULT
) by connect-
ing a resistor (R
TIM
) from TIM to GND. t
FAULT
can be
calculated by the following equation:
t
FAULT
= (166ns / ? x R
TIM
The t
FAULT
programmed time duration must be chosen
according to the total capacitance load connected to
the 12G_ and 3.3G_ pins. To properly power up the
main supply outputs, the following constraints need to
be taken:
t
SU
e (V
GATE
x C
LOAD
) / I
CHG
where t
SU
= 2 x t
FAULT
and where:
"  I
CHG
= 5礎(chǔ).
"  V
GATE
= 4.8V +V
12VIN
for 12G_ and V
GATE
= 6.8V
+V
3.3VIN
for 3.3G_.
"  C
LOAD
is the total capacitance load at the gate.
Maximum and minimum values for R
TIM
are 500?and
500k? respectively. Leave TIM floating for a default
t
FAULT
of 10ms.
Timeout Period (t
POR_HL
)
t
POR_HL
is the time from when the gate voltages of all
outputs of a slot reach their power-good threshold to
when PWRGD_ pulls low. Program the POR timeout
period (t
POR
) by connecting a resistor (R
PORADJ
) from
PORADJ to GND. t
POR_HL
can be calculated by the fol-
lowing equation:
t
POR_HL
= (2.5祍 / ? x R
PORADJ
Maximum and minimum values for R
PORADJ
are 500?/DIV>
and 500k? respectively. Leave PORADJ floating for a
default t
POR
of 150ms. Connect PORADJ to GND in
order to completely skip the power-on delay time prior
to the PWRGD_ assertion.
Component Selection
Select the external n-channel MOSFET according to the
applications current requirement. Limit the switch
power dissipation by choosing a MOSFET with an
R
DS_ON
low enough to have a minimum voltage drop at
full load. High R
DS_ON
causes larger output ripple if
there are pulsed loads. High R
DS_ON
can also trigger
an external undervoltage fault at full load. Determine
the MOSFETs power-rating requirement to accommo-
date a short-circuit condition on the board during start-
up. Table 3 lists the MOSFETs and sense resistor
manufacturers.