參數(shù)資料
型號(hào)： MAX5954LETX+T
廠商： Maxim Integrated
文件頁(yè)數(shù)： 19/22頁(yè)
文件大?。?/td> 1027K
描述： IC PCI EXP/HOT-PLUG CTRLR 36TQFN
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 2,500
類(lèi)型： 熱交換控制器
應(yīng)用： 通用型，PCI Express?
內(nèi)部開(kāi)關(guān)： 無(wú)
電源電壓： 3.3V，12V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 36-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 36-TQFN 裸露焊盤(pán)（6x6）
包裝： 帶卷 (TR)
Applications Information
Setting the Fault Timeout Period (t
FAULT
)
t
FAULT
is the time an overcurrent or overtemperature
fault must remain for the MAX5954 to disable the main
or auxiliary outputs. Program the fault timeout period
(t
FAULT
) by connecting a resistor (R
TIM
) from TIM to GND.
t
FAULT
can be calculated by the following equation:
t
FAULT
= 166ns / & x R
TIM
The t
FAULT
programmed time duration must be chosen
according to the total capacitance load connected to
12G and 3.3G. To properly power-up the main supply
outputs, the following constraints need to be taken:
where t
SU
= 2 x t
FAULT
and where:
1)  I
CHG
= 5礎(chǔ).
2)  V
GATE
= 18.4V for 12G and V
GATE
= 9.4V for 3.3G.
3)  C
LOAD
is the total capacitance load at the gate.
Maximum and minimum values for R
TIM
are 500k& and
500&, respectively. Leave TIM floating for a default
t
FAULT
of 11ms.
Setting the Power-On-Reset
Timeout Period (t
POR_HL
)
t
POR_HL
is the time from when the gate voltages of all
outputs reach their power-good threshold to when
PWRGD pulls low. Program the power-on-reset timeout
period (t
POR
) by connecting a resistor (R
PORADJ
) from
PORADJ to GND. t
POR_HL
can be calculated by the fol-
lowing equation:
t
POR_HL
= 2.5祍 / & x R
PORADJ
Maximum and minimum values for R
PORADJ
are 500k&
and 500&, respectively. Leave PORADJ floating for a
default t
POR
of 160ms.
Component Selection
Select the external n-channel MOSFET according to the
applications current requirement. Limit the switch
power dissipation by choosing a MOSFET with an
R
DS_ON
low enough to have a minimum voltage drop at
full load. High R
DS_ON
causes larger output ripple if
there are pulsed loads. High R
DS_ON
can also trigger an
external undervoltage fault at full load. Determine the
MOSFETs power rating requirement to accommodate a
short-circuit condition on the board during startup. Table
3 lists MOSFETs and sense-resistor manufacturers.
Additional External Gate Capacitance
External capacitance can be added from the gate of
the external MOSFETs to GND to slow down the dV/dt
of the 12V and 3.3V outputs.
Maximum Load Capacitance
Large capacitive loads at the 12V output, the 3.3V out-
put, and the 3.3V auxiliary output can cause a problem
when inserting discharged PCI cards into live back-
planes. A fault occurs if the time needed to charge the
capacitance of the board is greater than the typical
startup time (2 x t
FAULT
). The MAX5954 can withstand
large capacitive loads due to their adjustable startup
times and adjustable current-limit thresholds. Calculate
the maximum load capacitance as follows:
V
OUT
is either the 3.3V output, the 12V output, or the
3.3V auxiliary output.
C
t
I
V
LOAD
SU    LIM
<
?/DIV>
t
V
C
I
SU
GATE
LOAD
H
e
?/DIV>
Single PCI Express, Hot-Plug
Controller
______________________________________________________________________________________   19
Table 3. Component Manufacturers
COMPONENT
MANUFACTURER
PHONE
WEBSITE
Vishay-Dale
402-564-3131
www.vishay.com
Sense Resistor
IRC
704-264-8861
www.irctt.com
Fairchild
888-522-5372
www.fairchildsemi.com
International Rectifier
310-322-3331
www.irf.com
Motorola
602-244-3576
www.mot-sps.com/ppd/
MOSFETs
Vishay-Siliconix

www.vishay.com
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