參數(shù)資料
型號: MAX5952CUAX+
廠商: Maxim Integrated
文件頁數(shù): 29/50頁
文件大?。?/td> 1006K
描述: IC PSE CNTRLR FOR POE 36-SSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 30
類型: 以太網(wǎng)供電控制器(PoE)
應用: 遠程外設(工業(yè)控制,相機,數(shù)據(jù)訪問)
內(nèi)部開關:
工作溫度: 0°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 36-BSOP(0.295",7.50mm 寬)
供應商設備封裝: 36-SSOP
包裝: 管件
High-Power, Quad, PSE Controller
for Power-Over-Ethernet
______________________________________________________________________________________   29
The MAX5952 continuously monitors the power sup-
plies and sets the appropriate bits in the supply event
register (Table 12). V
DD_OV
/V
EE_OV
is set to 1 whenev-
er V
DD
/V
EE
exceeds its overvoltage threshold.
V
DD_UV
/V
EE_UV
is set to 1 whenever V
DD
/V
EE
falls
below its undervoltage threshold.
OSC_FAIL is set to 1 whenever the amplitude of the
oscillator signal at the OSC_ input falls below a level
that might compromise the AC disconnect detection
function. OSC_FAIL generates an interrupt only if at
least one of the ACD_EN (R13h[7:4]) bits is set high.
A thermal shutdown circuit monitors the temperature of
the die and resets the MAX5952 if the temperature
exceeds +150癈. TSD is set to 1 after the MAX5952
returns to normal operation. TSD is also set to 1 after
every UVLO reset.
When V
DD
and/or |V
EE
| is below its UVLO threshold, the
MAX5952 is in reset mode and securely holds all ports
off. When V
DD
and |V
EE
| rise to above their respective
UVLO thresholds, the device comes out of reset as
soon as the last supply crosses the UVLO threshold.
The last supply corresponding UV and UVLO bits in the
supply event register is set to 1.
A 1 in any supply event registers bits forces R00h[7] to
1. As with any of the other events register, the supply
event register has two addresses. When read through
the R0Ah address, the content of the register is left
unchanged. When read through the CoR R0Bh
address, the register content is cleared. A reset sets
R0Ah/R0Bh to 10100001b if V
DD
comes up after V
EE
or
to 10010100b if V
EE
comes up after V
DD
.
Table 12. Supply Event Register
ADDRESS =
0Ah
0Bh
SYMBOL
BIT
R/W
R/W
DESCRIPTION
TSD
7
R
CoR
Overtemperature shutdown
V
DD_OV
6
R
CoR
V
DD
 overvoltage condition
V
DD_UV
5
R
CoR
V
DD
 undervoltage condition
V
EE_UVLO
4
R
CoR
V
EE
 undervoltage lockout condition
V
EE_OV
3
R
CoR
V
EE
 overvoltage condition
V
EE_UV
2
R
CoR
V
EE
 undervoltage condition
OSC_FAIL
1
R
CoR
Oscillator amplitude is below limit
V
DD_UVLO
0
R
CoR
V
DD
 undervoltage lockout condition
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