High-Power, Quad, PSE Controller
for Power-Over-Ethernet
18   ______________________________________________________________________________________
Powered Device Classification
(PD Classification)
During the PD classification mode, the MAX5952 forces
a probe voltage (-18V) at DET_ and measures the cur-
rent into DET_. The measured current determines the
class of the PD.
After each classification cycle, the device sets the
CL_END_ bit (R04h/05h[7:4]) high and reports the clas-
sification results in the status registers R0Ch[6:4],
R0Dh[6:4], R0Eh[6:4], and R0Fh[6:4]. The CL_END_ bit
is reset to low when read through register R05h or after
a port reset. Both status registers, R04h, and R05h are
cleared after the port powers down. Table 2 shows the
IEEE 802.3af requirement for a PSE classifying a PD at
the power interface (PI).
The MAX5952 supports high power beyond the IEEE
802.3af standard by providing additional classifications
(Class 5 and ping-pong classification).
Powered State
When the MAX5952 enters a powered state, the t
START
and t
DISC
timers are reset. Before turning on the port
power, the MAX5952 checks if any other port is not
turning on and if the t
FAULT
timer is zero. Another
check is performed if the ACD_EN bit is set, in this
case the OSC_FAIL bit must be low (oscillator is okay)
for the port to be powered.
If these conditions are met, the MAX5952 enters startup
where it turns on power to the port. An internal signal,
POK_, asserts high when V
OUT
is within 2V from V
EE
.
PGOOD_ status bits are set high if POK_ stays high
longer than t
PGOOD
. PGOOD immediately resets when
POK goes low.
The PG_CHG_ bit sets when a port powers up or down.
PWR_EN sets when a port powers up and resets when
a port shuts down. The port shutdown timer lasts 0.5ms
and prevents other ports from turning off during that
period, except in the case of emergency shutdowns
(RESET = L, RESET_IC = H, V
EEUVLO,
V
DDUVLO,
and
TSHD).
The MAX5952 always checks the status of all ports before
turning off. A priority logic system determines the order to
prevent the simultaneous turn-on or turn-off of the ports.
The port with the lesser ordinal number gets priority over
the others (i.e., port 1 turns on first, port 2 second, port 3
third and port 4 fourth). Setting PWR_OFF_ high turns off
power to the corresponding port.
Table 2. PSE Classification of a PD (Table
33-4 of the IEEE 802.3af)
MEASURED I
CLASS
(mA)
CLASSIFICATION
0 to 5
Class 0
> 5 and < 8
May be Class 0 and 1
8 to 13
Class 1
> 13 and < 16
May be Class 1 or 2
16 to 21
Class 2
> 21 and < 25
May be Class 2 or 3
25 to 31
Class 3
> 31 and < 35
May be Class 3 or 4
35 to 45
Class 4
> 45 and < 51
May be Class 4 or 5
51 to 68
Class 5
Figure 1. Detection, Classification, and Power-Up Port
Sequence
OUT_
-4V
-9V
-18V
-48V
t
t
DETI
t
DETII
t
CLASS
150ms
150ms
21.3ms
0V
0V
80ms