參數(shù)資料
型號: MAX5950ETJ+
廠商: Maxim Integrated
文件頁數(shù): 18/28頁
文件大?。?/td> 552K
描述: IC PWM CTRL HOT-SW 12V 32TQFN-EP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 60
類型: 熱交換控制器
應用: 通用型,PCI Express?
內部開關:
電源電壓: 8 V ~ 16 V,±5V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFQFN 裸露焊盤
供應商設備封裝: 32-TQFN-EP(5x5)
包裝: 管件
12V PWM Controller with Hot-Swap
18   ______________________________________________________________________________________
Input-Capacitor Selection
The discontinuous input current of the buck converter
causes large input ripple currents, therefore the input
capacitor must be carefully chosen to withstand the
input ripple current and maintain the input voltage rip-
ple within design requirements. The total voltage ripple
is the sum of V
Q
(caused by the capacitor discharge)
and V
ESR
(caused by the ESR of the input capacitor),
which peaks at the end of the ON cycle. Calculate the
input capacitance and ESR required for a specified rip-
ple using the following equations:
I
LOAD(MAX)
is the maximum output current, I
P-P
is the peak-
to-peak inductor current, and f
SW
is the switching frequency.
The MAX5950 includes UVLO hysteresis to avoid possi-
ble unintentional chattering during turn-on. Use addition-
al bulk capacitance if the input source impedance is
high. When the input voltage is near the UVLO, addition-
al input capacitance helps avoid possible undershoot
below the UVLO threshold during transient loading.
Output-Capacitor Selection
The allowed output voltage ripple and the maximum
deviation of the output voltage during load steps deter-
mine the required output capacitance and its ESR. The
output ripple is mainly composed of V
Q
(caused by
the capacitor discharge) and V
ESR
(caused by the
voltage drop across the equivalent series resistance
(ESR) of the output capacitor). The equations for calcu-
lating the peak-to-peak output voltage ripple are:
V
ESR
and V
Q
are not directly additive since they are
out of phase from each other. If using ceramic capaci-
tors, which generally have low ESR, V
Q
dominates. If
using electrolytic capacitors, V
ESR
dominates.
The allowable deviation of the output voltage during
load transients also affects the choice of output capaci-
tance, its ESR, and its equivalent series inductance
(ESL). The output capacitor supplies the load current
during a load step until the controller responds with a
greater duty cycle. The response time (t
RESPONSE
)
depends on the closed-loop bandwidth of the converter
(see the Compensation Design Guidelines section).
The resistive drop across the output capacitors ESR,
the drop across the capacitors ESL, and the capacitor
discharge cause a voltage droop during the load step.
Use a combination of low-ESR tantalum/aluminum elec-
trolyte and ceramic capacitors for better load transient
and voltage-ripple performance. Surface-mount capac-
itors and capacitors in parallel help reduce the ESL.
Keep the maximum output-voltage deviation below the
tolerable limits of the electronics being powered. Use
the following equations to calculate the required ESR,
ESL, and capacitance value during a load step:
where I
STEP
is the load step, t
STEP
is the rise time of the
load step, and t
RESPONSE
is the response time of the
controller.
Setting the Current Limit
Connect a 25k& to 175k& resistor, R
ILIM
, from ILIM to
AGND to program the valley current-limit threshold from
50mV to 350mV. ILIM sources 20礎 out to R
ILIM
. The
resulting voltage divided by 10 is the valley current-limit
threshold.
The MAX5950 uses a valley current-sense method for
current limiting. The voltage drop across the low-side
MOSFET due to its on-resistance is used to sense the
inductor current. The voltage drop across the low-side
MOSFET at the valley point and at I
LOAD(MAX)
is:
R
DS(ON)
is the on-resistance of the low-side MOSFET,
which is temperature dependent, I
LOAD(MAX)
is the
maximum DC load current, and I
P-P
is the peak-to-
peak inductor current.
V
R
T    I
I
VALLEY
DS ON
LOAD MAX
P  P
=
?/DIV>

?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>

(    )
(
)
( )

2
ESR
V
I
COUT
I
t
V
ESL
V
t
I
ESR
STEP
STEP    RESPONSE
Q
ESL    STEP
STEP
=
=
?/DIV>
=
?/DIV>







V
I
C
f
V
ESR
I
Q
P  P
OUT    SW
ESR
P  P
=
?/DIV>
?/DIV>
=
?/DIV>


8
2
 
 
 
(
)
(
)
(
)
_
_
_
ESR
V
I
I
C
I
V
V
V    f
here
I
V
V
V
V
f
L
ESR
LOAD MAX
P  P
IN
LOAD MAX
OUT
PWM  IN
Q    SW
P  P
PWM  IN
OUT
OUT
PWM  IN    SW
=
+
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=

?/DIV>
?/DIV>
?/DIV>






2
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