參數(shù)資料
型號(hào): MAX5949BESA+T
廠商: Maxim Integrated
文件頁(yè)數(shù): 8/18頁(yè)
文件大小: 186K
描述: IC CNTRLR HOT SWAP 8-SOIC
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
電源電壓: -20 V ~ -80 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
Detailed Description
The MAX5949A/MAX5949B are integrated hot-swap
controllers for -48V power systems. They allow circuit
boards to be safely hot plugged into a live backplane
without causing a glitch on the power-supply rail. When
circuit boards are inserted into a live backplane without
hot-swap control, the bypass capacitors at the input of
the boards power module or switching power supply
can draw large inrush currents as they charge. The
inrush currents can cause glitches on the system
power-supply rail and damage components on the
board.
The MAX5949A/MAX5949B provide a controlled turn-on
to circuit cards, preventing glitches on the power-supply
rail and damage to board connectors and components.
Both the MAX5949A and MAX5949B provide undervolt-
age, overvoltage, and overcurrent protection. The
MAX5949A/MAX5949B ensure the input voltage is sta-
ble and within tolerance before applying power to the
load. The devices also provide protection against input
voltage steps. During an input voltage step, the
MAX5949A/MAX5949B limit the current drawn by the
load to a safe level without turning off power to the load.
-48V Hot-Swap Controllers
with External R
SENSE
8  _______________________________________________________________________________________
Pin Description
PIN
MAX5949A  MAX5949B
NAME
FUNCTION
1

PWRGD
Power-Good Signal Output. PWRGD is an active-low open-drain status output referenced
to V
EE
. PWRGD is latched low when V
DRAIN
 - V
EE
 d V
DL
 and V
GATE
 > (V
GATE
 - V
GH
),
indicating a power-good condition. PWRGD is open drain otherwise.

1
PWRGD
Power-Good Signal Output. PWRGD is an active-high open-drain status output referenced
to DRAIN. PWRGD latches in a high-impedance state when V
DRAIN
 - V
EE
 d V
DL
and
V
GATE
 > (V
GATE
 - V
GH
), indicating a power-good condition. PWRGD is pulled low to
DRAIN otherwise.
2
2
OV
Input Pin for Overvoltage Detection. OV is referenced to V
EE
. When OV is pulled above the
V
OVH
 voltage, the GATE pin is immediately pulled low. The GATE pin remains low until the
OV pin voltage reduces to V
OVL
.
3
3
UV
Input Pin for Undervoltage Detection. UV is referenced to V
EE
. When UV is pulled above the
V
UVH
 voltage, the GATE is enabled. When UV is pulled below V
UVL
, GATE is pulled low.
UV is also used to reset the circuit breaker after a fault condition. To reset the circuit
breaker, pull UV below V
UVL
. The reset command can be issued immediately after a fault
condition; however, the device does not restart until a t
OFF
 delay time has elapsed after
the fault.
4
4
V
EE
Device Negative Power-Supply Input. Connect to the negative power-supply rail.
5
5
SENSE
Current-Sense Voltage Input. Connect to an external sense resistor and the external
MOSFET source. The voltage drop across the external sense resistor is monitored to detect
overcurrent or short-circuit fault conditions. Connect SENSE to V
EE
 to disable the current-
limiting feature.
6
6
GATE
Gate-Drive Output. Connect to the gate of the external n-channel MOSFET.
7
7
DRAIN
Output-Voltage Sense Input. Connect to the output-voltage node (drain of the external
n-channel MOSFET).
8
8
V
DD
Positive Power-Supply Rail Input. This is the power ground in the negative-supply voltage
system. Connect to the higher potential of the power-supply inputs.
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