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參數資料
| 型號： | MAX5949BESA+T |
| 廠商： | Maxim Integrated |
| 文件頁數： | 3/18頁 |
| 文件大?。?/td> | 186K |
| 描述： | IC CNTRLR HOT SWAP 8-SOIC |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | -20 V ~ -80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
-48V Hot-Swap Controllers
with External R
SENSE
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
EE
= 0V, V
DD
= 48V, T
A
= -40癈 to +85癈. Typical values are at T
A
= +25癈, unless otherwise noted.) (Notes 2, 5)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PWRGD OUTPUT SIGNAL REFERENCED TO DRAIN
DRAIN Input Bias Current
I
DRAIN
V
DRAIN
= 48V
10
80
250
礎
D RAIN Thr
eshol
d for P
ow er - G ood
V
DL
V
DRAIN
- V
EE
threshold for power-good
condition, DRAIN decreasing
1.1
1.4
2.0
V
GATE High Threshold
V
GH
V
GATE
- V
GATE
threshold for power-good
condition, V
GATE
- V
GATE
decreasing
1.0
1.4
2.0
V
PWRGD, PWRGD Output
Leakage
I
OH
PWRGD (MAX5949A) = 80V, V
DRAIN
= 48V,
PWRGD (MAX5949B) = 80V, V
DRAIN
= 0V
10
礎
PWRGD Output Low Voltage
V
OL
V
PWRGD
- V
EE;
V
DRAIN
- V
EE
< V
DL
,
I
SINK
= 5mA (MAX5949A)
0.11
0.4
V
PWRGD Output Low Voltage
V
OL
V
PWRGD
- V
DRAIN
; V
DRAIN
= 5V,
I
SINK
= 1mA (MAX5949B)
0.11
0.4
V
AC PARAMETERS
OV High to GATE Low
t
PHLOV
Figures 2a, 3
0.5
祍
UV Low to GATE Low
t
PHLUV
Figures 2a, 4
0.4
祍
OV Low to GATE High
t
PLHOV
Figures 2a, 3
4
祍
UV High to GATE High
t
PLHVL
Figures 2a, 4
5.5
祍
SENSE High to GATE Low
t
PHLSENSE
Figures 2a, 5a
1
3
祍
Current Limit to GATE Low
t
PHLCB
Figures 2b, 5b
350
500
650
祍
MAX5949A, Figures 2a, 6a
1.8
DRAIN Low to PWRGD Low
DRAIN Low to (PWRGD - DRAIN)
High
t
PHLDL
MAX5949B, Figures 2a, 6a
3.4
祍
MAX5949A, Figures 2a, 6b
1.6
GATE High to PWRGD Low
GATE High to (PWRGD - DRAIN)
High
t
PHLGH
MAX5949B, Figures 2a, 6b
2.5
祍
TURN-OFF
Latch-Off Period
t
OFF
(Note 4)
51
64
78
ms
Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to V
EE
,
unless otherwise specified.
Note 3: Current into V
DD
with UV = 3V, OV = DRAIN = PWRGD = SENSE = V
EE
, GATE = open.
Note 4: Minimum duration of GATE pulldown following a circuit-breaker fault. The circuit breaker can be reset during this time by
toggling UV low, but the GATE pulldown does not release until t
OFF
has elapsed.
Note 5: Limits are 100% tested at T
A
= +25癈 and +85癈. Limits at -40癈 are guaranteed by design.
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