參數(shù)資料
型號(hào): MAX5878EGK
廠(chǎng)商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): DAC
英文描述: 16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs
中文描述: PARALLEL, WORD INPUT LOADING, 16-BIT DAC, QCC68
封裝: 10 X 10 MM, MO-220, QFN-68
文件頁(yè)數(shù): 16/18頁(yè)
文件大?。?/td> 511K
代理商: MAX5878EGK
M
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
16
______________________________________________________________________________________
capacitors. Ferrite beads with additional decoupling
capacitors forming a pi-network could also improve per-
formance.
The analog and digital power-supply inputs AV
DD3.3
,
AV
CLK
, and DV
DD3.3
allow a +3.135V to +3.465V sup-
ply voltage range. The analog and digital power-supply
inputs AV
DD1.8
and DV
DD1.8
allow a +1.71V to +1.89V
supply voltage range.
The MAX5878 is packaged in a 68-pin QFN-EP pack-
age, providing greater design flexibility, increased ther-
mal efficiency, and optimized DAC AC performance.
The EP enables the use of necessary grounding tech-
niques to ensure highest performance operation.
Thermal efficiency is not the key factor, since the
MAX5878 features low-power operation. The exposed
pad ensures a solid ground connection between the
DAC and the PC board’s ground layer.
The data converter die attaches to an EP lead frame with
the back of this frame exposed at the package bottom
surface, facing the PC board side of the package. This
allows for a solid attachment of the package to the PC
board with standard infrared reflow (IR) soldering tech-
niques. A specially created land pattern on the PC board,
matching the size of the EP (6mm x 6mm), ensures the
proper attachment and grounding of the DAC. Designing
vias into the land area and implementing large ground
planes in the PC board design allow for the highest per-
formance operation of the DAC. Use an array of at least 4
x 4 vias (
0.3mm diameter per via hole and 1.2mm pitch
between via holes) for this 68-pin QFN-EP package.
Connect the MAX5878 exposed paddle to GND.
Vias
connect the land pattern to internal or external copper
planes. Use as many vias as possible to the ground
plane to minimize inductance.
Static Performance Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from either a best straight-line fit
(closest approximation to the actual transfer curve) or a
line drawn between the end points of the transfer func-
tion, once offset and gain errors have been nullified.
For a DAC, the deviations are measured at every indi-
vidual step.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step height and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees a
monotonic transfer function.
Offset Error
The offset error is the difference between the ideal and
the actual offset current. For a DAC, the offset point is
the average value at the output for the two midscale
digital input codes with respect to the full scale of the
DAC. This error affects all codes by the same amount.
Gain Error
A gain error is the difference between the ideal and the
actual full-scale output voltage on the transfer curve,
after nullifying the offset error. This error alters the slope
of the transfer function and corresponds to the same
percentage error in each step.
MAX5878
16
OUTIP/OUTQP
OUTIN/OUTQN
DATA15–DATA0
GND
25
50
25
OUTP
OUTN
Figure 8. Differential Output Configuration
MAX5878
16
OUTIP/OUTQP
OUTIN/OUTQN
DATA15–DATA0
0.1
μ
F
AV
DD1.8
DV
DD1.8
0.1
μ
F
0.1
μ
F
0.1
μ
F
AV
DD3.3
DV
DD3.3
0.1
μ
F
AV
CLK
BYPASSING—DAC LEVEL
*BYPASS EACH POWER-SUPPLY PIN INDIVIDUALLY.
Figure 9. Recommended Power-Supply Decoupling and
Bypassing Circuitry
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