參數(shù)資料
型號(hào)： MAX5878EGK
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： DAC
英文描述： 16-Bit, 250Msps, High-Dynamic-Performance, Dual DAC with LVDS Inputs
中文描述： PARALLEL, WORD INPUT LOADING, 16-BIT DAC, QCC68
封裝： 10 X 10 MM, MO-220, QFN-68
文件頁(yè)數(shù)： 12/18頁(yè)
文件大小： 511K
代理商： MAX5878EGK
M
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
12
______________________________________________________________________________________
The MAX5878’s reference circuit (Figure 2) employs a
control amplifier to regulate the full-scale current
I
OUTFS
for the differential current outputs of the DAC.
Calculate the full-scale output current as follows:
where I
OUTFS
is the full-scale output current of the
DAC. R
SET
(located between FSADJ and DACREF)
determines the amplifier’s full-scale output current for
the DAC. See Table 1 for a matrix of different I
OUTFS
and R
SET
selections.
Analog Outputs (OUTIP, OUTIN, OUTQP,
OUTQN)
Each MAX5878 DAC outputs two complementary cur-
rents (OUTIP/N, OUTQP/N) that operate in a single-
ended or differential configuration. A load resistor
converts these two output currents into complementary
single-ended output voltages. A transformer or a differ-
ential amplifier configuration converts the differential
voltage existing between OUTIP (OUTQP) and OUTIN
(OUTQN) to a single-ended voltage. If not using a
transformer, the recommended termination from the
output is a 25
termination resistor to ground and a
50
resistor between the outputs.
To generate a single-ended output, select OUTIP (or
OUTQP) as the output and connect OUTIN (or OUTQN)
to GND. SFDR degrades with single-ended operation
or increased output swing. Figure 3 displays a simpli-
fied diagram of the internal output structure of the
MAX5878.
Clock Inputs (CLKP, CLKN)
The MAX5878 features flexible differential clock inputs
(CLKP, CLKN) operating from a separate supply
(AV
CLK
) to achieve optimum jitter performance. Drive
the differential clock inputs from a single-ended or a
differential clock source. For single-ended operation,
drive CLKP with a logic source and bypass CLKN to
GND with a 0.1μF capacitor.
CLKP and CLKN are internally biased to AV
CLK
/ 2. This
facilitates the AC-coupling of clock sources directly to
the device without external resistors to define the DC
level. The dynamic input resistance from CLKP and
CLKN to ground is 5k
.
I
V
R
OUTFS
REFIO
SET
×
×
=
32
1
1
2
16
Table 1. I
OUTFS
and R
SET
Selection
Matrix Based on a Typical +1.200V
Reference Voltage
R
SET
(
)
FULL-SCALE
CURRENT I
OUTFS
(mA)
2
5
10
15
20
CALCULATED
19.2k
7.68k
3.84k
2.56k
1.92k
1% EIA STD
19.1k
7.5k
3.83k
2.55k
1.91k
OUTIP
OUTIN
+1.2V
REFERENCE
CURRENT-SOURCE
ARRAY DAC
REFIO
FSADJ
R
SET
I
REF
10k
DACREF
1
μ
F
I
REF
= V
REFIO
/ R
SET
GND
Figure 2. Reference Architecture, Internal Reference
Configuration
I
OUT
I
OUT
OUTIN OUTIP
CURRENT
SOURCES
CURRENT
SWITCHES
AV
DD
Figure 3. Simplified Analog Output Structure
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