參數(shù)資料
型號(hào): MAX5875
廠商: Maxim Integrated Products, Inc.
英文描述: Quadruple Line Driver 14-CDIP -55 to 125
中文描述: 16位、200Msps、高動(dòng)態(tài)性能、雙路DAC,CMOS輸入
文件頁(yè)數(shù): 9/18頁(yè)
文件大?。?/td> 511K
代理商: MAX5875
M
16-Bit, 250Msps, High-Dynamic-Performance,
Dual DAC with LVDS Inputs
_______________________________________________________________________________________
9
Pin Description
PIN
1
2
3
4
5
6
7
8
9
NAME
B4N
B3P
B3N
B2P
B2N
B1P
B1N
B0P
B0N
FUNCTION
Complementary Data Bit 4
Data Bit 3
Complementary Data Bit 3
Data Bit 2
Complementary Data Bit 2
Data Bit 1
Complementary Data Bit 1
Data Bit 0 (LSB)
Complementary Data Bit 0 (LSB)
10, 12, 13, 15,
20, 23, 26, 27,
30, 33, 36
GND
Ground
11
DV
DD3.3
Digital Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1μF
capacitor to GND.
14, 21, 22, 31,
32
AV
DD3.3
Analog Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass each pin with
a 0.1μF capacitor to GND.
16
REFIO
Reference I/O. Output of the internal 1.2V precision bandgap reference. Bypass with a 1μF
capacitor to GND. REFIO can be driven with an external reference source. See Table 1.
17
FSADJ
Full-Scale Adjust Input. This input sets the full-scale output current of the DAC. For a 20mA full-
scale output current, connect a 2k
resistor between FSADJ and DACREF. See Table 1.
18
DACREF
Current-Set Resistor Return Path. Internally connected to GND.
Do not use as an external
ground connection.
19, 34
AV
DD1.8
Analog Supply Voltage. Accepts a 1.71V to 1.89V supply voltage range. Bypass each pin with a
0.1μF capacitor to GND.
24
25
28
29
OUTQN
OUTQP
OUTIN
OUTIP
Complementary Q-DAC Output. Negative terminal for current output.
Q-DAC Output. Positive terminal for current output.
Complementary I-DAC Output. Negative terminal for current output.
I-DAC Output. Positive terminal for current output.
35
AV
CLK
Clock Supply Voltage. Accepts a 3.135V to 3.465V supply voltage range. Bypass with a 0.1μF
capacitor to GND.
37
CLKN
Complementary Converter Clock Input. Negative input terminal for differential converter clock.
Internally biased to AV
CLK
/ 2.
38
CLKP
Converter Clock Input. Positive input terminal for differential converter clock. Internally biased to
AV
CLK
/ 2.
39
TORB
Two’s-Complement/Binary Select Input. Set TORB to a CMOS-logic-high level to indicate a two’s-
complement input format. Set TORB to a CMOS-logic-low level to indicate a binary input format.
TORB has an internal pulldown resistor.
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