參數(shù)資料
型號: MAX5874EGK+D
廠商: Maxim Integrated Products
文件頁數(shù): 3/16頁
文件大小: 0K
描述: IC DAC 14BIT 200MSPS DUAL 68-QFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 30
設(shè)置時間: 14ns
位數(shù): 14
數(shù)據(jù)接口: 并聯(lián)
轉(zhuǎn)換器數(shù)目: 2
電壓電源: 模擬和數(shù)字
功率耗散(最大): 300mW
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN 裸露焊盤(10x10)
包裝: 管件
輸出數(shù)目和類型: 4 電流,單極
采樣率(每秒): 200M
產(chǎn)品目錄頁面: 1398 (CN2011-ZH PDF)
MAX5874
14-Bit, 200Msps, High-Dynamic-Performance,
Dual DAC with CMOS Inputs
______________________________________________________________________________________
11
CMOS-Compatible Digital Inputs
Input Data Format Select (TORB,
DORI)
The TORB input selects between two’s-complement or
binary digital input data. Set TORB to a CMOS-logic-
high level to indicate a two’s-complement input format.
Set TORB to a CMOS-logic-low level to indicate a binary
input format.
The
DORI input selects between a dual-port (parallel) or
single-port (interleaved) DAC. Set
DORI high to configure
the MAX5874 as a dual-port DAC. Set
DORI low to con-
figure the MAX5874 as a single-port DAC. In dual-port
mode, connect SELIQ to ground.
CMOS DAC Inputs (A13/B13–A0/B0, XOR, SELIQ)
The MAX5874 latches input data on the rising edge of
the clock in a user-selectable two’s-complement or
binary format. A logic-high voltage on TORB selects
two’s-complement and a logic-low selects offset
binary format.
The MAX5874 includes a single-ended, CMOS-compati-
ble XOR input. Input data (all bits) are compared with the
bit applied to XOR through exclusive-OR gates. Pulling
XOR high inverts the input data. Pulling XOR low leaves
the input data noninverted. By applying a previously
encoded pseudo-random bit stream to the data input and
applying decoding to XOR, the digital input data can be
decorrelated from the DAC output, allowing for the trou-
bleshooting of possible spurious or harmonic distortion
degradation due to digital feedthrough on the printed
circuit board (PCB).
A13/B13–A0/B0, XOR, and SELIQ are latched on the ris-
ing edge of the clock. In single-port mode (
DORI pulled
low) a logic-high signal on SELIQ directs the B13–B0
data onto the I-DAC inputs. A logic-low signal at SELIQ
directs data to the Q-DAC inputs. In dual-port (parallel)
mode (
DORI pulled high), data on pins A13–A0 are
directed onto the Q-DAC inputs and B13–B0 are directed
onto the I-DAC inputs.
Power-Down Operation (PD)
The MAX5874 also features an active-high power-
down mode that reduces the DAC’s digital current
consumption from 22mA to less than 2A and the ana-
log current consumption from 77mA to less than 2A.
Set PD high to power down the MAX5874. Set PD low
for normal operation.
When powered down, the power consumption of the
MAX5874 is reduced to less than 14W. The MAX5874
requires 10ms to wake up from power-down and enter a
fully operational state. The PD integrated pulldown resistor
activates the MAX5874 if PD is left floating.
OUTIP
OUTIN
1.2V
REFERENCE
CURRENT-SOURCE
ARRAY DAC
REFIO
FSADJ
RSET
IREF
10k
DACREF
1F
IREF = VREFIO / RSET
Figure 2. Reference Architecture, Internal Reference
Configuration
IOUT
OUTIN OUTIP
CURRENT
SOURCES
CURRENT
SWITCHES
AVDD
Figure 3. Simplified Analog Output Structure
Table 2. DAC Output Code Table
DIGITAL INPUT CODE
OFFSET
BINARY
TWO’S
COMPLEMENT
OUT_P
OUT_N
00 0000 0000 0000 10 0000 0000 0000
0
IOUTFS
01 1111 1111 1111 00 0000 0000 0000 IOUTFS / 2 IOUTFS / 2
11 1111 1111 1111 01 1111 1111 1111
IOUTFS
0
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