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Shutdown mode offers the most dramatic power sav-
ings by shutting down all the analog sections of the
MAX5865 and placing the ADCs
’
digital outputs in tri-
state mode. When the ADCs
’
outputs transition from tri-
state to on, the last converted word is placed on the
digital outputs. The DACs
’
digital bus inputs must be
zero or OV
DD
because the bus is not internally pulled
up. The DACs
’
previously stored data is lost when com-
ing out of shutdown mode. The wake-up time from shut-
down mode is dominated by the time required to
charge the capacitors at REFP, REFN, and COM. In
internal reference mode and buffered external refer-
ence mode, the wake-up time is typically 40μs to enter
Xcvr mode, 20μs to enter Rx mode, and 40μs to enter
Tx MODE.
In idle mode, the reference and clock distribution cir-
cuits are powered, but all other functions are off. The
ADCs
’
outputs are forced to tri-state. The DACs
’
digital
bus inputs must be zero or OV
DD
, because the bus is
not internally pulled up. The wake-up time from the idle
mode is 10μs required for the ADCs and DACs to be
fully operational. When the ADCs
’
outputs transition
from tri-state to on, the last converted word is placed
on the digital outputs. In the idle mode, the supply cur-
rent is lowered if the clock input is set to zero or OV
DD
;
however, the wake-up time extends to 40μs.
In standby mode, only the ADCs
’
reference is powered;
the rest of the device
’
s functions are off. The pipeline
ADCs are off and DA0 to DA7 are in tri-state mode. The
DACs
’
digital bus inputs must be zero or OV
DD
because the bus is not internally pulled up. The wake-
up time from standby mode to the Xcvr mode is domi-
nated by the 40μs required to activate the pipeline
ADCs and DACs. When the ADC outputs transition from
tri-state to active, the last converted word is placed on
the digital outputs.
The serial digital interface is a standard 3-wire connec-
tion compatible with SPI/QSPI
/MICROWIRE/DSP
interfaces. Set
CS
low to enable the serial data loading
at DIN. Following
CS
high-to-low transition, data is shift-
ed synchronously, MSB first, on the rising edge of the
serial clock (SCLK). After 8 bits are loaded into the seri-
al input register, data is transferred to the latch.
CS
must transition high for a minimum of 80ns before the
next write sequence. The SCLK can idle either high or
low between transitions.
Figure 5
shows the detailed
timing diagram of the 3-wire serial interface.
M
Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
______________________________________________________________________________________
17
QSPI is a trademark of Motorola, Inc.
Table 3. MAX5865 Operation Modes
FUNCTION
DESCRIPTION
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
Shutdown
D evi ce shutd ow n. RE F i s off, AD C s ar e
off, and the AD C b us i s tr stated D AC s
ar e off and the D AC i np ut b us m ust b e
set to zer o or OV
D D
.
X
X
X
X
X
0
0
0
Idle
REF and CLK are on, ADCs are off,
and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
set to zero or OV
DD
.
X
X
X
X
X
0
0
1
Rx
REF is on, ADCs are on; DACs are off,
and the DAC input bus must be set to
zero or OV
DD
.
X
X
X
X
X
0
1
0
Tx
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are on.
X
X
X
X
X
0
1
1
Xcvr
REF is on, ADCs and DACs are on.
X
X
X
X
X
1
0
0
Standby
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are off and the
DAC input bus must be set to zero or
OV
DD
.
X
X
X
X
X
1
0
1
X
= Don’t care.