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General Description
The MAX5865 ultra-low-power, highly integrated analog
front end is ideal for portable communication equipment
such as handsets, PDAs, WLAN, and 3G wireless termi-
nals. The MAX5865 integrates dual 8-bit receive ADCs
and dual 10-bit transmit DACs while providing the high-
est dynamic performance at ultra-low power. The ADCs’
analog I-Q input amplifiers are fully differential and
accept 1V
P-P
full-scale signals. Typical I-Q channel
phase matching is
±
0.2
°
and amplitude matching is
±
0.05dB. The ADCs feature 48.4dB SINAD and 70dBc
spurious-free dynamic range (SFDR) at f
IN
= 5.5MHz and
f
CLK
= 40MHz. The DACs’ analog I-Q outputs are fully
differential with
±
400mV full-scale output, and 1.4V com-
mon-mode level. Typical I-Q channel phase matching is
±
0.15
°
and gain matching is
±
0.05dB. The DACs also
feature dual 10-bit resolution with 72dBc SFDR, and
57dB SNR at f
OUT
= 2.2MHz and f
CLK
= 40MHz.
The ADCs and DACs operate simultaneously or indepen-
dently for frequency-division duplex (FDD) and time-divi-
sion duplex (TDD) modes. A 3-wire serial interface
controls power-down and transceiver modes of opera-
tion. The typical operating power is 75.6mW at f
CLK
=
40Msps with the ADCs and DACs operating simultane-
ously in transceiver mode. The MAX5865 features an
internal 1.024V voltage reference that is stable over the
entire operating power-supply range and temperature
range. The MAX5865 operates on a +2.7V to +3.3V ana-
log power supply and a +1.8V to +3.3V digital I/O power
supply for logic compatibility. The quiescent current is
8.5mA in idle mode and 1μA in shutdown mode. The
MAX5865 is specified for the extended (-40°C to +85°C)
temperature range and is available in a 48-pin thin QFN
package.
Applications
Narrowband/Wideband CDMA Handsets
and PDAs
Fixed/Mobile Broadband Wireless Modems
3G Wireless Terminals
Ordering Information
Features
o
Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs
o
Ultra-Low Power
75.6mW at f
CLK
= 40MHz (Transceiver Mode)
64mW at f
CLK
= 22MHz (Transceiver Mode)
Low-Current Idle and Shutdown Modes
o
Excellent Dynamic Performance
48.4dB SINAD at f
IN
= 5.5MHz (ADC)
70dB SFDR at f
OUT
= 2.2MHz (DAC)
o
Excellent Gain/Phase Match
±
0.2
°
Phase,
±
0.05dB Gain at f
IN
= 5.5MHz (ADC)
o
Internal/External Reference Option
o
+1.8V to +3.3V Digital Output Level (TTL/CMOS
Compatible)
o
Multiplexed Parallel Digital Input/Output for
ADCs/DACs
o
Miniature 48-Pin Thin QFN Package (7mm
7mm)
o
Evaluation Kit Available (Order MAX5865EVKIT)
M
Ultra-Low-Power, High-Dynamic-
Performance, 40Msps Analog Front End
________________________________________________________________
Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
ADC
ADC
IA+
IA-
QA+
QA-
ID+
ID-
QD+
QD-
REFP
COM
REFN
DIN
SCLK
CS
REFIN
DAC
DAC
ADC
OUTPUT
MUX
DAC
INPUT
MUX
CLK
DA0–DA7
DD0–DD9
MAX
5865
REF AND
BIAS
SERIAL
INTERFACE
AND SYSTEM
CONTROL
Functional Diagram
19-2916; Rev 1; 10/03
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-PACKAGE
MAX5865ETM
-40
°
C to +85
°
C
48 Thin QFN-EP*
(7mm x 7mm)
MAX5865E/D
-40
°
C to +85
°
C
Dice**
*
EP = Exposed paddle.
**
Contact factory for dice specifications.
Pin Configuration appears at end of data sheet.