參數(shù)資料
型號(hào)： MAX5864ETM
廠(chǎng)商： MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi)： 無(wú)繩電話(huà)/電話(huà)
英文描述： Ultra-Low-Power, High-Dynamic- Performance, 22Msps Analog Front End
中文描述： TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC48
封裝： 7 X 7 MM, 0.80 MM HEIGHT, TQFN-48
文件頁(yè)數(shù)： 18/26頁(yè)
文件大?。?/td> 2079K
代理商： MAX5864ETM
M
Mode Recovery Timing
Figure 6
shows the mode recovery timing diagram.
T
WAKE
is the wake-up time when exiting shutdown, idle,
or standby mode and entering into Rx, Tx, or Xcvr
mode. t
ENABLE
is the recovery time when switching
between any Rx, Tx, or Xcvr mode. t
WAKE
or t
ENABLE
is
the time for the ADC to settle within 1dB of specified
SINAD performance and DAC settling to 10 LSB error.
t
WAKE
or t
ENABLE
times are measured after the 8-bit
serial command is latched into the MAX5864 by
CS
transition high. t
ENABLE
for Xcvr mode is dominated by
the DAC wake-up time. The recovery time is 10μs to
switch between Xcvr, Tx, or Rx modes. The recovery
time is 40μs to switch from shutdown or standby mode
to Xcvr mode.
System Clock Input (CLK)
CLK input is shared by both the ADCs and DACs. It
accepts a CMOS-compatible signal level set by OV
DD
from 1.8V to V
DD
. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). Specifically,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide the lowest possible jitter.
Any significant clock jitter limits the SNR performance
of the on-chip ADCs as follows:
where f
IN
represents the analog input frequency and
t
AJ
is the time of the clock jitter.
SNR
t
t
IN
AJ
=
×
×
×
×
20
1
2
log
π
Ultra-Low-Power, High Dynamic-
Performance, 22Msps Analog Front End
18
______________________________________________________________________________________
Figure 5. 3-Wire Serial Interface Timing Diagram
MSB
CS
SCLK
DIN
LSB
t
CSW
t
CS
t
CP
t
CSS
t
CL
t
CH
t
DS
t
DH
Figure 6. MAX5864 Mode Recovery Timing Diagram
CS
SCLK
DIN
ID/QD
DAO
–
DA7
8-BIT DATA
ADC DIGITAL OUTPUT.
SINAD SETTLES WITHIN 1dB
DAC ANALOG OUTPUT. OUTPUT
SETTLES TO 10 LSB ERROR
t
WAKE, SD, ST_ (Rx)
OR t
ENABLE,
R
x
t
WAKE, SD, ST_ (Tx)
OR t
ENABLE,
T
X
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX5864ETM+ 功能描述:ADC / DAC多通道 10-Bit 2Ch 22Msps CODEC/AFE RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5864ETM+T 功能描述:ADC / DAC多通道 10-Bit 2Ch 22Msps CODEC/AFE RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5864ETM-T 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5865ETM 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5865ETM+ 功能描述:ADC / DAC多通道 10-Bit 2Ch 40Msps CODEC/AFE RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類(lèi)型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
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