參數(shù)資料
型號(hào)： MAX5863
廠商： Maxim Integrated Products, Inc.
英文描述： Quadruple Differential Line Receiver 16-CDIP -55 to 125
中文描述： 超低功耗、高動(dòng)態(tài)性能、7.5Msps模擬前端
文件頁(yè)數(shù)： 15/26頁(yè)
文件大?。?/td> 1673K
代理商： MAX5863
ADC System Timing Requirements
Figure 3
shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channel IA
(CHI) and channel QA (CHQ) are simultaneously sam-
pled on the rising edge of the clock signal (CLK) and
the resulting data is multiplexed at the DA0
–
DA7 out-
puts. CHI data is updated on the rising edge and CHQ
data is updated on the falling edge of the CLK.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for CHI and 5.5
clock cycles for CHQ.
Dual 10-Bit DAC
The 10-bit DACs are capable of operating with clock
speeds up to 7.5MHz. The DAC
’
s digital inputs,
DD0
–
DD9, are multiplexed on a single 10-bit bus. The
voltage reference determines the data converters
’
full-
scale output voltages. See the
Reference Configurations
section for setting reference voltage. The DACs utilize a
current-array technique with a 1mA (with 1.024V refer-
ence) full-scale output current driving a 400
internal
resistor resulting in a
±
400mV full-scale differential out-
put voltage. The MAX5863 is designed for differential
output only and is not intended for single-ended appli-
cation. The analog outputs are biased at 1.4V common
mode and designed to drive a differential input stage
with input impedance
≥
70k
. This simplifies the analog
interface between RF quadrature upconverters and the
MAX5863. RF upconverters require a 1.3V to 1.5V com-
mon-mode bias. The internal DC common-mode bias
eliminates discrete level-setting resistors and code-gen-
erated level-shifting while preserving the full dynamic
range of each transmit DAC.
Table 2
shows the output
voltage vs. input code.
M
Ultra-Low-Power, High-Dynamic
Performance, 7.5Msps Analog Front End
______________________________________________________________________________________
15
Figure 3. ADC System Timing Diagram
t
DOQ
t
DOI
5 CLOCK-CYCLE LATENCY (CHI), 5.5 CLOCK-CYCLE LATENCY (CHQ)
DA0
–
DA7
D0Q
D1I
D1Q
D2I
D2Q
D3I
D3Q
D4I
D4Q
D5I
D5Q
D6I
D6Q
CHI
CHQ
CLK
Figure 2. ADC Transfer Function
INPUT VOLTAGE (LSB)
-1
-126 -125
256
V
REF
2 x V
REF
1 LSB =
V
REF
= V
REFP
- V
REFN
V
REF
V
R
V
R
0
+1
-127
+126
+128
+127
-128
+125
(COM)
(COM)
O
0000 0000
0000 0001
0000 0010
0000 0011
1111 1111
1111 1110
1111 1101
0111 1111
1000 0000
1000 0001
相關(guān)PDF資料
PDF描述
MAX5863ETM 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
MAX5864 Quadruple Differential Line Receiver 16-CDIP -55 to 125
MAX5864ETM Ultra-Low-Power, High-Dynamic- Performance, 22Msps Analog Front End
MAX5865 Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End
MAX5865ETM Ultra-Low-Power, High-Dynamic- Performance, 40Msps Analog Front End
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX5863ETM 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5863ETM+ 功能描述:ADC / DAC多通道 10-Bit 2Ch 7.5Msps CODEC/AFE RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5863ETM+T 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5863ETM-T 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX5864ETM 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-40
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