參數(shù)資料
型號(hào)： MAX5852
廠商： Maxim Integrated Products, Inc.
英文描述： Quadruple 2-Input Exclusive-OR Gates 14-CDIP -55 to 125
中文描述： 雙路、8位、165Msps、電流輸出DAC
文件頁(yè)數(shù)： 6/18頁(yè)
文件大?。?/td> 1290K
代理商： MAX5852
M
Dual, 8-Bit, 165Msps, Current-Output DAC
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(AV
DD
= DV
DD
= CV
DD
= 3V, AGND = DGND = CGND = 0, f
DAC
= 165Msps, differential clock, external reference, V
REF
= 1.2V,
I
FS
= 20mA, output amplitude = 0dB FS, differential output, T
A
= T
MIN
to T
MAX
, unless otherwise noted. T
A
≥
+25°C guaranteed by
production test. T
A
< +25°C guaranteed by design and characterization. Typical values are at T
A
= +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
PD = 0 to V
OUT
Stable Time
(Coming Out of Power-Down)
t
SHDN
500
μs
Maximum Clock Frequency at
CLKXP/CLKXN Input
f
CLK
165
200
MHz
Clock High Time
Clock Low Time
t
CXH
t
CXL
CLKXP or CLKXN input
CLKXP or CLKXN input
1.5
1.5
ns
ns
CLKXP Rise to CLK Output Rise
Delay
t
CDH
DCE
= 0
2.7
ns
CLKXP Fall to CLK Output Fall
Delay
t
CDL
DCE
= 0
2.7
ns
Note 1:
Including the internal reference voltage tolerance and reference amplifier offset.
Note 2:
f
DAC
= 165Msps, f
OUT
= 10MHz.
Note 3:
Measured single-ended with 50
load and complementary output connected to AGND.
Note 4:
Guaranteed by design, not production tested.
TO OUTPUT
PIN
5pF
0.5mA
0.5mA
1.6V
Figure 1. Load Test Circuit for CLK Outputs
相關(guān)PDF資料
PDF描述
MAX5852ETL Quadruple 2-Input Exclusive-OR Gates 14-CFP -55 to 125
MAX5858 Quadruple 2-Input Exclusive-OR Gates 14-CDIP -55 to 125
MAX5858ECM Dual, 10-Bit, 300Msps, Current-Output DAC with 4x/2x/1x Interpolation Filters
MAX5863 Quadruple Differential Line Receiver 16-CDIP -55 to 125
MAX5863ETM 5V High-Speed RS-232 Transceivers with 0.1uF Capacitors
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