參數(shù)資料
型號(hào): MAX5534ETC
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: DAC
英文描述: Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs
中文描述: DUAL, PARALLEL, WORD INPUT LOADING, 660 us SETTLING TIME, 12-BIT DAC, QCC12
封裝: 4 X 4 MM, 0.80 MM HEIGHT, MO-220, TQFN-12
文件頁數(shù): 6/24頁
文件大小: 1554K
代理商: MAX5534ETC
M
Dual, Ultra-Low-Power,
12-Bit, Voltage-Output DACs
6
_______________________________________________________________________________________
Note 1:
Linearity is tested within codes 96 to 4080.
Note 2:
Offset is tested at code 96.
Note 3:
Gain is tested at code 4095. For the MAX5534/MAX5535, FB_ is connected to its respective OUT_.
Note 4:
Guaranteed by design. Not production tested.
Note 5:
V
DD
must be a minimum of 1.8V.
Note 6:
Outputs can be shorted to V
DD
or GND indefinitely, provided that package power dissipation is not exceeded.
Note 7:
Optimal noise performance is at 2nF load capacitance.
Note 8:
Thermal hysteresis is defined as the change in the initial +25°C output voltage after cycling the device from T
MAX
to T
MIN
.
Note 9:
All digital inputs at V
DD
or GND.
Note 10:
Load = 10k
in parallel with 100pF, V
DD
= 5V, VREF = 4.096V (MAX5532/MAX5534) or V
REF
= 3.9V (MAX5533/MAX5535).
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA= TMINto TMAX, unless otherwise noted. Typical values are at TA= +25
°
C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (V
DD
= 1.8V to 5.5V )
Serial Clock Frequency
DIN to SCLK Rise Setup Time
DIN to SCLK Rise Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS
Pulse-Width High
SCLK Rise to
CS
Rise Hold Time
CS
Fall to SCLK Rise Setup Time
SCLK Fall to
CS
Fall Setup
CS
Rise to SCK Rise Hold Time
f
SCLK
t
DS
t
DH
t
CH
t
CL
t
CSW
t
CSH
t
CSS
t
CSO
t
CS1
0
24
0
40
40
150
0
30
0
30
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
相關(guān)PDF資料
PDF描述
MAX5535ETC Dual, Ultra-Low-Power, 12-Bit, Voltage-Output DACs
MAX5580BETP Buffered, Fast-Settling, Quad, 12-/10-/8-Bit, Voltage-Output DACs
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